January 21, 2014, 7:49 am
Hi,
I have an issue with HPS hard DDR3 calibration on the Cyclone V SoC device. I have two boards (the same PCB), one with a single DDR3 device fitted (1Gb x 16) and the other with three devices fitted (1Gb x 40). Both show the same symptom. The preloader fails at during the sdram_calibration_full routine and I am get the following output from the UART.
SEQ.C: CALIBRATION FAILED
SEQ.C: Calibration Summary
SEQ.C: Calibration Failed
SEQ.C: Error Stage : 1
SEQ.C: Error Substage : 1
SEQ.C: Error Group : 0
I am under the impression that this is the very first stage of calibration and that this is a guaranteed read fail?
I am using an LP2998 DDR regulator to provide the termination and reference voltages. I've noticed that the VREF is sitting at around 850mV when I turn the board on and then this reduces to 805mV when I run the preloader. The Vtt rail is sitting at 745mV.
I have searched and found a known problem with the VREF pin on these HPS devices -
http://www.altera.co.uk/support/kdb/...02013_752.html
but I am using 13.1 with update 1 applied. Is this still a known issue?
I'm not entirely sure that this is my problem, but I think it must be something fairly fundamental for the calibration to fail at first stage.
Thanks.
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January 21, 2014, 8:24 am
I've noticed that each time I reboot or power cycle the SoC, it appears to have a different MAC address. I thought that the MAC address should be fixed for a device and was not reprogrammable. On further investigation, it appears the EMAC register map has 128 MAC address registers. Does linux build use these? Is there actually a hard coded address in the MAC or does it require an external MAC address EEPROM to read from?
I'm using yocto project linux version 3.9.0, is there a known issue with reading the MAC address? Or is the MAC address supposed to be programmed by software each boot-up?
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January 21, 2014, 2:08 pm
I'd like to develop a Cyclone III app (possibly with the NIOS II processor) for a new design. Is a paid license required for distribution ? It's not clear from the Quartus Subscription vs. Web comparison pdf.
Apologies in advance for the "newbie" question
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January 21, 2014, 3:18 pm
I just got a Terasic DE4 Development and Education board. I need very simple sample for Quartus 12 and Qsys to play with. Does anybody know where can I find the samples.
Best,
Sean
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January 22, 2014, 12:32 am
Hi
How do I send data from Nios 2 processor to HDL in quartus. I need to send data such as a variable i.e. a=5; or array[20] to the vhdl side in quartus. How do I set up a shared memory space. I am using the Altera DE3 board. Please explain to me carefully, I have around 4 months of vhdl and fpga experience.
Regards
Reigngt09
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January 22, 2014, 12:42 am
I would like to know if its possible to transfer data from Nios II to a DDR.
I understand the transfer has to a Avalon MM interface .
My question is it there an Altera IP which can be used initiate the data transfer.
Or Is there an example which I can generate and simulate ??
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January 22, 2014, 1:55 am
Hi everyone,
I want to implement basic averaging block in dsp builder and control it by using qsys.
I have added five register field to obtain data from qsys and then I add them by using five inputs adder then multiply the result with 0.2.
Finally, I write the result of the multiplication to the RegOut block.
I have not used channel in and channel out blocks as in the example of demo_regs.mdl. Therefore, I do not know the latency of my dsp builder system.
If I read the RegOut block soon after writing the data registers I read wrong result because the dsp builder system has not calculated the result yet.
How can I know the latency of my dsp builder system and how can I understand finishing of the calculation?
Thanks,
Omer
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January 22, 2014, 2:42 am
As a follow up to this thread....
http://www.alteraforum.com/forum/showthread.php?t=34049
...this board is having a re-spin and I'd _really_ like to use a cheap eprom that works at 2.5V, that has been proven.
Does anyone have any recommendations?
I've only started searching so will come back with anything I find.
Thanks for any pointers,
Nial
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January 22, 2014, 4:20 am
Hello!
What role does the port tx_cons_cred_sel? How to see the result of his shift?
Victor.
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January 22, 2014, 4:28 am
Hi,
I plan to use a Cyclone V FPGA in combination with a LPDDR2 RAM from Micron.
The Cyclone V FPGA needs 1.07V .. 1.13V for the core, and 1.14V .. 1.26V for the 1.2V-IO-Pins.
The Micron RAM needs nearly the same voltage (1.14 .. 1.30V) for it's 1.2V logic IO and core.
I don't use the FPGA at the highest possible switching speeds, that applies to the RAM, too. Used fmax is 200MHz.
(a) What effects do I have to consider if I power the FPGA core with 1.2V instead of 1.1V to save one voltage regulator? (BTW: 1.2V is far away from the absolute maximum rating of 1.43V...)
(b) What effects do I have to consider if I drive the 1.2V IO pins with 1.1V VCCIO? (I'am using 1.2V HSUL voltage referenced IO standard, and VREF will be scaled down to fit 0.5xVCCIO).
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January 22, 2014, 4:32 am
Hi,
I've been using the Arria II GX FPGA development board for 6 month without any problem but encountered a problem yesterday. When I power up the board, the Load LED illuminates, but shortly it goes out. Then the Error red LED illuminates. When I try to do the auto-detect in the programmer, the FPGA is shown as UNKNOWN device in both methods of using embedded USB blaster and external USB Blaster cable. I also tried both with and without the MAX II CPLD EPM2210 System Controller in the JTAG chain) and got the same problem.
I am in the middle of testing my design and desperately need help !!!
Many man thanks,
Scott
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January 22, 2014, 4:37 am
Hello,
I have a problem with written program VHDL to LCD on Altera DE2 with 2 lines.
I have done on 7-seg and LED, and I want the same inscription on LCD witch is now and working on 7-seg.
LCD is ready. Ports and pins are declared.
Code:
LCD_POWERON: out STD_LOGIC; -- power on
LCD_ENABLE: out STD_LOGIC; -- enable
LCD_BL: out STD_LOGIC; -- back light
LCD_RS: out STD_LOGIC;
LCD_RW: out STD_LOGIC;
LCD_DATA: inout STD_LOGIC_VECTOR (0 to 7)
And this is fragment of code
Code:
if (WL = '0') then -- button WL
LEDY <= "000000000000";
LD7 <= "0111111"; LD6 <= "0111111"; LD5 <= "0111111"; LD4 <= "0111111";
LD3 <= "0111111"; LD2 <= "0111111"; LD1 <= "0111111"; LD0 <= "0111111";
licznik <= 0;
zdarzenie <= 0;
else
if (falling_edge(CLK)) then
if (zdarzenie = 0) then -- stop (2s)
LEDY <= "000000000000";
LD7 <= "1000110"; LD6 <= "0100100"; LD5 <= "1111111"; LD4 <= "1111111";
LD3 <= "0010010"; LD2 <= "0000111"; LD1 <= "1000000"; LD0 <= "0001100";
licznik <= 0;
zdarzenie <= 0;
if (licznik <= TIME_2) then
licznik <= licznik + 1;
else
licznik <= 0;
zdarzenie <= 1;
end if;
elsif (zdarzenie = 1) then -- forward (4.5s)
LEDY <= "000000000001";
LD7 <= "1000110"; LD6 <= "0100100"; LD5 <= "0100001"; LD4 <= "0100011";
LD3 <= "0001100"; LD2 <= "0101111"; LD1 <= "0100100"; LD0 <= "1111111";
if (licznik <= TIME_4_5) then
licznik <= licznik + 1;
else
licznik <= 0;
zdarzenie <= 2;
end if;
elsif (zdarzenie = 2) then -- right (1s)
LEDY <= "000000100100";
LD7 <= "1000110"; LD6 <= "0100100"; LD5 <= "0100011"; LD4 <= "0000011";
LD3 <= "0001100"; LD2 <= "0101111"; LD1 <= "1111111"; LD0 <= "1111111";
if (licznik <= TIME_1) then
licznik <= licznik + 1;
else
licznik <= 0;
zdarzenie <= 3;
end if;
And I need the same inscription like on 7-seg, but now on LCD.
Please help.
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January 22, 2014, 5:09 am
I've been working through my troubles with the UDP offload example and have successfully implemented this as described in the Wiki. I am now pushing into my next portion of the project, injecting my payload via an Avalon streaming source that will replace the PRBS generator.
Setup:
Mixed width DCFIFO instantiated to accept 8-bit data and output 32-bit data as required by the UDP Payload inserter.
PRBS Generator verilog as a base for the module
Issues:
1. I have my Source Valid tied to (SW enable and Sink Ready) -- Doing this my module will respond with a valid signal every time the UDP payload and following chain are "ready". This works OK except: I am passing invalid data as my FIFO does not respond quickly, therefore, my packets have 4 or 5 copies of the same data until a new word is processed.
2. To mitigate the issue I've tried delaying the valid signal to assert upon FIFO valid, a signal indicating new data is ready. This works for a period of time, and then the UDP payload chain "stalls". The ready bit of all items drops to '0'. This amount of time seems variable depending on the amount of delay associated with asserting the valid signal. My latest attempt gets to 1014 / 1024 bytes. previous attempts had 512, 516, ie random amounts.
My investigation into the avalon streaming interface seems that what I am doing is completely valid. If a sink ready = '1' and source valid = '0' no data is transmitted, but that only seems to hold true to a point. TSE MAC is auto negotiating to communicate at 1000Mbps; however, I attempted this at 100Mbps as well just in case my FIFO valid delay was causing some link speed issues?? Obviously not the case.
Please any help would be greatly appreciated, I must be doing something wrong but I can't figure out what and why the avalon streaming breaks down if I delay my source valid signal.
Thanks!
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January 22, 2014, 5:22 am
Hi,
I am trying to write a program where I get an asynchronous callback once a kernel has finished and I am stuck. May be a trivial thing (or not?) but I am running out of ideas.
In OpenCL 1.1 and higher, one can call clSetEventCallback(), passing it an event and a user function that gets called once the associated kernel is done. However, Altera's OpenCL api is 1.0 and this function apparently doesn't exist.
A second way I thought of is to call clEnqueueNativeKernel(), passing it a command ququeue and a user "kernel" function. As I understood it, a native kernel is just a normal C/C++ function that should get executed on the CPU. So what I had expected is that once it's the enqueued native kernel's time in the Queue, the driver would just call the function. However, this seems to be the wrong assumption because I get a "CL_INVALID_OPERATION" error and clGetDeviceInfo tells me that the FPGA cannot execute a native kernel (the CL_EXEC_NATIVE_KERNEL flag is 0 when asking for the execution capabilities).
So one workaround would be to install the intel opencl sdk and open a second platform/device, create a queue there and order the kernels cross-platform through their event objects. But a) this really seems overkill and b) I am not even sure if that is supposed to work.
So my question: is there any straight forward way how I can tell the OpenCL driver to call a C/C++ callback function on the host once some (non native) kernel finished?
Thanks,
Christoph
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January 22, 2014, 5:52 am
Hi,
I need some help with triggering an application restart from bootloader.
In my system I have an on-chip RAM (where bootloader resides) and an SRAM where application will be running. The reset vector is located in the onchip RAM.
If I jump to the reset vector location, the Nios reboots but starts from the application and does not execute the bootloader.
How can I force the execution of the bootloader?
Thanks!
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January 22, 2014, 7:01 am
Hi Everyone,
I am thinking using PLL for clock derivation,but I have a problem for PLL inputs.There are 11 inputs for PLL and I wanna use multiplexer (created in FPGA) before PLL to select one of them as a input for PLL.but As I see PLL don't accept multiplexer output as input. I think I have to route Muxtiplexer output to FPGA output and then , I have to take it as a input from another FPGA pin.So,I can use this signal for PLL input. but I don't want to waste FPGA pins.
Do you any idea How can I use multiplexer outputs for PLL inputs ? If you share your ideas ,I really appreciate this.
Thanks in advance
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January 22, 2014, 7:08 am
Hi,
I've been using the Arria II GX FPGA development board for 6 month without any problem but encountered a problem yesterday. When I power up the board, the Load LED illuminates as flash configuration is loading, but shortly it goes out. Then the Error red LED illuminates to indicate flash configuration has failed. When I try to do the auto-detect in the programmer, the FPGA is shown as UNKNOWN device in both methods of using embedded USB blaster and external USB Blaster cable. I also tried both with and without the MAX II CPLD EPM2210 System Controller in the JTAG chain) and got the same problem.
I tried to add file .sof to program the FPGA anyway but got the following error msg:
Info (209060): Started Programmer operation at Tue Jan 21 17:22:44 2014
Error (209015): Can't configure device. Expected JTAG ID code 0x025040DD for device 1, but found JTAG ID code 0x025FC0DD.
Error (209012): Operation failed
Info (209061): Ended Programmer operation at Tue Jan 21 17:22:44 2014
I am in the middle of testing my design and desperately need help !!!
Many man thanks,
Scott
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January 22, 2014, 8:27 am
Hello to all,
We are using both the subscription and free web versions of the QuartusII software. And I have been using the Quartus II software since Version 6.0. I have never seen the the issue we are now seeing in version 13.1 was released.
The hard core VHDL designers tend to scoff at me when they find out that I use both VHDL and Block Diagram File (BDF) supported by Quartus. At my company, we like the graphic way that BDF files display our the design hierarchy as opposed to searching through Port Maps when debugging our designs. Plus our engineering technicians love me because I give them block diagrams. Well enough of my handicaps.
This question is for any Quartus II Block Diagram File users that may be out there. If I want to move components around in a BDF file, first I have to select the components to be moved. After I select the components, and I move the mouse pointer to grab the logic to be moved, Quartus creates a copy of the logic and pastes it directly on top of the existing logic. I have the same problem selecting and moving primitives like the pin symbol or for that matter, any component that I attempt to move. Then only work-around to this is to use the directional keys on my keyboard.
Has anyone heard of this one?
Perhaps there is a setting that I can turn off or on to tell Quartus to not generate the bogus copied components?
Best Regards,
RonM, SMTS
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January 22, 2014, 9:42 am
Hi,
I'm using Cyclone III on DE0, Quartus II.
I was wondering where/how are the groupings of SW[0] to SW[9] done and combined into one signal of 10 bits named SW?
Initially, I defined SW[0] to the appropriate pin myself and got no complaint.
Later, I used import on the default .qsf file from Altera website and I get the complaint "some pins have incomplete i/o assignment" if I try to use
module top (SW[0], LEDG[0])
instead of
module top (SW, LEDG)
I would just like to understand what is going on.
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January 22, 2014, 10:25 am
In Quartus 13.1, the ALTPLL wizard isn't located under the "PLL" Directory.
For some reason, it is under the "IO" directory. :confused:
I know this will be fixed in 14.0. I searched this forum and couldn't find anything regarding this. Hopefully somebody else will find this on a search and not waste their whole evening trying to rebuild Quartus. This is not your installation.
Herman
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