How to access fpgamgrregs/gpi registerfrom FPGA fabric?!?

April 3, 2014, 7:03 am

≪ Previous: DDR3 Uniphy altera example design error in Modelsim

Hi,

I'm lookin for a failsafe way to read a system ID from the HPS (-> OS = Linux) even if there is nor configuration in the FPGA. my latest idea is to use the gpi register of the FPGA manager, but I don't know how to access it from the FPGA fabric. Any hints?

You might ask yourself: Why am I doing this? Why am I not using the System ID component of QSys? Well, what if I design a QSys system that has a System ID componenat on the say LWHPS2FPGA Bridge at address 0x0. Let's say, I forget to configure the FPGA with that system (or something goes seriously wrong during configuration of the FPGA). Now, If I try to access address 0x0 from the Linux OS either with mmap() or ioread32(), and there is no System ID component on that address, I already observed that both the mmap() and ioread32() calls block the whole system so that I'm forced to reboot the linux system.
I imagine that if I write a defined value (my system ID) to the gpi register of the FPGA manager, that would be easy to read out by my Linux system and I can easily determine if the expected design is loaded into the FPGA. If not, then the Linux system can continue to work and it can react in some way to that fault.

So how do i write to that gpi register from the FPGA fabric?

Thanks,
Maik

↧

Entity output bit selection

April 3, 2014, 7:28 am

≫ Next: Programming the Stratix V GS development board

≪ Previous: How to access fpgamgrregs/gpi registerfrom FPGA fabric?!?

Hello guys !!

I'm working with an entity that has a 32 bits ouput and this entity is instantiated in my top_designì. My top_design has to ouput the 16 LSB ot this lower level entity. So i was wondering if it's possible to do something like:

my_lower_lev_entity_inst : work.my_lower_lev_entity
PORT MAP(......, ouput(15 downto 0)=> my_top_design_output)

Is it a correct way ?? I see only a warning compiling th top in that way..

Thank you !

↧

Programming the Stratix V GS development board

April 3, 2014, 7:47 am

≫ Next: compairing signals inside a clock sensitive process

≪ Previous: Entity output bit selection

Hi,

Is the only way to program the Stratix V GS development board throught the usb-Blaster II cable or can I just use the usb cable that hooks up to the
mini-usb on the front of the board. My office mate told me on some of the other boards he has used he just needed the mini-usb to program it.

Thanks in advance,
Oscar

↧

compairing signals inside a clock sensitive process

April 3, 2014, 8:15 am

≫ Next: DQS frequency of a Cyclone IV EP4CE40F29C8 with 2x DDR2

≪ Previous: Programming the Stratix V GS development board

Hi!

This code is a simplification of the actual code. clk is a 50Mhz clock signal, busy is an of chip signal coming from one of the pins. (GPIO on the DE2-115 developing board)
busy_i is an internal signal and n is just a signal used to count clock periodes.

process(clk)
begin
busy_i <= busy;
n <= n + 1;
if((busy_i = '1') and (busy = '0')) then
state <= s_RD;
elsif(n = 1500) then
state <= s_RD;
end if;
end process;

This code wil not always detect the falling edge on busy(the difference in busy_i and busy).
That is also why i included the elsif statment, so that after a given count of clock periodes the state signal vil be forced the value of s_RD.

So my question is: Is this some bad coding from me, or could it be somthing with the fact that busy is an of chip signal - maybe a combination of the two?

Realy appreciate some thoughts! Maybe someone have hade a similar issue?

Thanks!
-electrosmith

↧

DQS frequency of a Cyclone IV EP4CE40F29C8 with 2x DDR2

April 3, 2014, 11:26 am

≫ Next: Which Linux zip program can be used to unzip Altera zip files?

≪ Previous: compairing signals inside a clock sensitive process

Hello,

A EP4CE40F29C8 (core voltage 1.2V) uses two Micron MT47H32M16 in parallel in x8 mode on bottom banks 3 & 4 creating a 32bit bus DDR2. Using ALTMEMPHY HPCII at half rate. Pin assignments are correct and it compiles fine with no errors. There are however four critical warnings concerning the four DQS pins:

Critical Warning (165040): The DQS pin "DDR_DQS[3]" has a frequency of 160.0 MHz which is not supported at location PIN AF26
Info (165017): Location PIN AF26 can support a maximum DQS frequency of 134.01 MHz

The same warning is given for all four DQS pins placed in: AF26, AE18, AE10, AD7

The maximum frequency quartus suggests, is the frequency when using row banks. Changing the speed grade to C7 gives the same warning with a suggested frequency of 150MHz, which is again the frequency when using row banks. According to the datasheet and the External Memory Interface Spec Estimator tool by altera, the C8 grade supports DDR2 up to 167MHz on column banks.

It is not possible to run DDR2 (MT47H32M16) at 133MHz because the minimum tRTP time of 7.5ns cannot be achieved.

What is going wrong here?

Thnx in advance!

↧

Which Linux zip program can be used to unzip Altera zip files?

April 3, 2014, 11:56 am

≫ Next: Porting DE_NET2 to NIOSII running on Quartus 12.1sp1 and QSYS

≪ Previous: DQS frequency of a Cyclone IV EP4CE40F29C8 with 2x DDR2

Which Linux zip program can be used to unzip Altera zip files like:

ftp://ftp.altera.com/outgoing/devkit..._v12.1.0.1.zip

Code:

$ file arriaVGT_5agtfd7kf40_fpga_v12.1.0.1.zip 

arriaVGT_5agtfd7kf40_fpga_v12.1.0.1.zip: Zip archive data, at least v2.0 to extract

$ unzip -v |head -1

UnZip 6.00 of 20 April 2009, by Info-ZIP.  Maintained by C. Spieler.  Send

$ unzip arriaVGT_5agtfd7kf40_fpga_v12.1.0.1.zip 

Archive:  arriaVGT_5agtfd7kf40_fpga_v12.1.0.1.zip

  End-of-central-directory signature not found.  Either this file is not

  a zipfile, or it constitutes one disk of a multi-part archive.  In the

  latter case the central directory and zipfile comment will be found on

  the last disk(s) of this archive.

So which Linux program can be used to unzip it?

gzip and bzip2 does not seem to work either. I was hoping that Altera would go for something like a gzip'ed tar file for other than Windows self extracting exe files.

↧

Porting DE_NET2 to NIOSII running on Quartus 12.1sp1 and QSYS

April 3, 2014, 5:08 pm

≫ Next: Triple Speed Ethernet and transceiver blocks

≪ Previous: Which Linux zip program can be used to unzip Altera zip files?

Hi,
I'm trying to port DE_NET2 to Quartus 12.1sp1 and QSYS.
I have created in QSYS dm9000a component based on DM9000A_IF.v file. The code:

Code:

module DM9000A_IF(    //    HOST Side

                    iDATA,

                    oDATA,

                    iCMD,

                    iRD_N,

                    iWR_N,

                    iCS_N,

                    iRST_N,

                    iCLK,

                    iOSC_50,

                    oINT,

                    //    DM9000A Side

                    ENET_DATA,

                    ENET_CMD,

                    ENET_RD_N,

                    ENET_WR_N,

                    ENET_CS_N,

                    ENET_RST_N,

                    ENET_INT,

                    ENET_CLK    );

//    HOST Side

input    [15:0]    iDATA;

input            iCMD;

input            iRD_N;

input            iWR_N;

input            iCS_N;

input            iRST_N;

input            iCLK;

input            iOSC_50;

output    [15:0]    oDATA;

output            oINT;

//    DM9000A Side

inout    [15:0]    ENET_DATA;

output            ENET_CMD;

output            ENET_RD_N;

output            ENET_WR_N;

output            ENET_CS_N;

output            ENET_RST_N;

output            ENET_CLK;

input            ENET_INT;



reg        [15:0]    TMP_DATA;

reg                ENET_CMD;

reg                ENET_RD_N;

reg                ENET_WR_N;

reg                ENET_CS_N;

reg                ENET_CLK;

reg        [15:0]    oDATA;

reg                oINT;



assign    ENET_DATA    =    ENET_WR_N    ?    16'hzzzz    :    TMP_DATA;



always@(posedge iCLK or negedge iRST_N)

begin

    if(!iRST_N)

    begin

        TMP_DATA     <=    0;

        ENET_CMD     <=    0;

        ENET_RD_N     <=    1;

        ENET_WR_N     <=    1;

        ENET_CS_N     <=    1;

        oDATA        <=    0;

        oINT        <=    0;

    end

    else

    begin

        oDATA        <=    ENET_DATA;

        oINT        <=    ENET_INT;

        TMP_DATA     <=    iDATA;

        ENET_CMD     <=    iCMD;

        ENET_CS_N     <=    iCS_N;

        ENET_RD_N     <=    iRD_N;

        ENET_WR_N     <=    iWR_N;

    end

end



always@(posedge iOSC_50)

ENET_CLK    <=    ~ENET_CLK;



assign    ENET_RST_N    =    iRST_N;



endmodule

Here's the componet overview:

dm9000_component1.jpg

Timing was taken from old DM9000A class.ptf.
Based on those settings I get in signal tap this results:

st_1.jpg

when executing this code on NIOS:

Code:

#define IO_addr     0

#define IO_data     1



iow(0x1E, 0x01);



void iow(unsigned int reg, unsigned int data)

{

 IOWR(DM9000A_BASE,IO_addr,reg);

 usleep(STD_DELAY);

 IOWR(DM9000A_BASE,IO_data,data);

}

Value of reg 0x1E goes to the bus.
Also CMD going up was rather strange. So in the second try I have changed address units WORD to SYMBOLS in my component. And here's the result:

st_3.jpg

Now I can even write the whole 16 bits at once, and CMD is gone. I suppose that it's not good that I get two 16 bit writes to the DM9000a. Perhaps it's related to the 32 bits that gets written by NIOS so it gives two clock cycles. I have provided only 16 bits, rest all zero. So my questions are:
1) How to make only one 16 bit write ?

2) The second IOWR(DM9000A_BASE,IO_data,data) - so writing the data (CMD should be high) never goes to the bus, CMD is always low. Any ideas why ?

st_4.jpg

I add DM9000A_hw.tcl packed in zip, so you can easily open it in QSYS and see my component. Also I have uploaded the whole project to Dropbox:

https://www.dropbox.com/s/6ru77wypta...ga_imgproc.rar

Thanks in advance,
Best regards,
madness

Attached Images

dm9000_component1.jpg (102.2 KB)
st_1.jpg (64.9 KB)
st_3.jpg (66.9 KB)
st_4.jpg (92.0 KB)

Attached Files

DM9000A_hw.zip (1.3 KB)

↧

Triple Speed Ethernet and transceiver blocks

April 3, 2014, 8:05 pm

≫ Next: SocKit for Ethernet project

≪ Previous: Porting DE_NET2 to NIOSII running on Quartus 12.1sp1 and QSYS

We have a Nios2/s processor running a triple speed ethernet (TSE) with a scatter gather DMA. Working off the of the triple speed ethernet example from altera for our board (DE4 Stratix IV board), there seems to be a missing option. When setting up the TSE, the option "Use Transceiver Block" does not exist, though all other settings match. Our system can send but is not receiving properly. What does this option do? Is there a new setting that replaces this option? (We are using a later version of Quartus than the example used).

This is the only salient difference we can currently find between our design and the example. What could be causing this issue?

Thank you in advanced.

↧

SocKit for Ethernet project

April 3, 2014, 11:27 pm

≫ Next: Booting Linux from SD card on SoCKit

≪ Previous: Triple Speed Ethernet and transceiver blocks

Hi. Has anybody tried to adapt standard Ethernet example for sockit or run it's own Ethernet project on this board?

↧

Booting Linux from SD card on SoCKit

April 4, 2014, 12:02 am

≫ Next: who used video and image processing component？not VIP suit!

≪ Previous: SocKit for Ethernet project

Hi There,

I have just got a SoCKit - I am rather inexperienced with FPGAs, ARM processors and Linux, so please bare with me!

I have been running through the getting started guides and come stuck with booting Linux from an SD card. I believe I have followed the instructions in SoCKit_Getting_Started_Guide.pdf and My_First_HPS.pdf correctly, but linux will not boot.

The error I am getting on power up (or with the command bootd) is:

Quote:

** Unable to use mmc 0:1 for fatload **
Wrong Image Format for bootm command
ERROR: can't get kernel image!

This is when using the pre-built Linux image ("Tools/Factory_SD_image/SoCKit_SD.img" on the SoCKit CD), loaded onto the SD card using Win32DiskImager (also on the CD).
I have tried:

Using the latest version of Win32DiskImager
Using a different SD card

Additional Information:
First SD card: 16GB, class 10
Second SD card: 2GB class 4 (Smaller capacity than suggested, all I have around to compare to)

Any suggestions, pointers or assistance is greatly appreciated!

EDIT: I note that the MSEL switch settings adviced in SoCKit_Getting_Started_Guide (page 24) are 0b01111 - however this is not listed as a valid setting in the user manual ??

Cheers,
Elliott

↧

who used video and image processing component？not VIP suit!

April 4, 2014, 1:14 am

≫ Next: Instantiating LPM Functions in VHDL: parallel adder

≪ Previous: Booting Linux from SD card on SoCKit

IT is AN654! WHEN I open reference project in QUARTUS 13.1 there is errors! so i need the lately an654.pdf！ so WHO can help me！

↧

Instantiating LPM Functions in VHDL: parallel adder

April 4, 2014, 1:16 am

≫ Next: Replacing IDE by Eclips

≪ Previous: who used video and image processing component？not VIP suit!

Hello guys...

I'm trying instatniating some altera MF directly in my top design.

From what I have understand I have two use two libraries:

Code:

library altera_mf;

use altera_mf.altera_mf.components.all;



library lpm;

use lpm.lpm_components.all;

The first libray is used to avoid the components declarations and the second is used to instantiate directly the lpm objects.

So, as I want to use a parallel adder, I wrote:

Code:

parallel_add_inst : parallale_add

GENERIC MAP(....)

PORT MAP(...);

By the way, looking at the Integer Arithmetic Megafunctions User
Guide, the port map of the parallel adder is:

Code:

data:in altera_mf_logic_2D(size - 1 downto 0,width- 1 downto 0);

clock : in std_logic := '1';

aclr : in std_logic := '0';

clken : in std_logic := '1';

result : out std_logic_vector(widthr - 1 downto 0));

So, how should I write the port map if I want to add two input signals (eg dataa[15..0] and datab[15..0]) ?

Thank you !

Have a nice day !

↧

Replacing IDE by Eclips

April 4, 2014, 2:09 am

≫ Next: Nios II Board support Package error

≪ Previous: Instantiating LPM Functions in VHDL: parallel adder

Hello every body;
I use the sd-card demonstration for the DE3-150 board from terasic, when I opened this demonstration by the Eclips I faced some errors about the "signedness", can I overcome this problem.
Thanks.

↧

Nios II Board support Package error

April 4, 2014, 5:01 am

≫ Next: EPM7128ELC84 fab/rev differences

≪ Previous: Replacing IDE by Eclips

hi,

this is Laxman, I am New to altera FPGA and i am using Quartus II for Cyclone II DE1 board.
I am creating BSP in NIOS II and It is compiling successfully but at the end of compilation it showing an error and that error screen shot is attached.can u please tell me what is this about and how to resolve this problem.

thanks and regards

Attached Files

errors.doc (204.5 KB)

↧

EPM7128ELC84 fab/rev differences

April 4, 2014, 5:21 am

≫ Next: Compile errors with Qsys generated verilog

≪ Previous: Nios II Board support Package error

We've been using EPM7128ELC84-200 since the 90s, shipped thousands of boards with no problems. It seems only "older" chips made in the US with 2 digit letter. 4 digit number lot number work fine and newer chips don't. I'm in the process of reviewing the datasheet and trying to get clues as to what's going on. I only have the .pof file which was compiled with an older development system prior to Quartus, or whatever it's called and hope I don't need to resurrect this project and recompile this thing. Fully understand the date and process markings as per Altera's PCN

Chased the possibility of counterfeit chips, improper programming, etc... purchased a batch of chips from ARROW here in NJ, a reputable distributor, which also don't work. Confirmed any chip with earlier date codes erases/reprograms and works

The CPLD does handle enable lines for a ROM connected to a DSP so I'm looking at startup problems, DSP access before the 7128 is "ready", powerup/reset timing, etc... but I would have thought moving to a later rev die or different fab of the 7128 would be seamless and just work.

I'm a XILINX guy and hoping someone here is familiar with this issue.

Thanks,
Phil

↧

Compile errors with Qsys generated verilog

April 4, 2014, 5:33 am

≫ Next: Quartus 13.1,Qsys Generation Error only with PLL

≪ Previous: EPM7128ELC84 fab/rev differences

Error (10162): Verilog HDL Object Declaration error at c5g_nios2_dram_daq_mem_if_lpddr2_emif_p0_acv_hard_ io_pads.v(289): can't declare implicit net "dqs_busout" because the current value of 'default_nettype is "none"

I get the above error when running analysis and elaboration on a qsys generated Nios II cpu which uses LPDDR2 RAM. This also occurs when I compile the demonstration application which comes with the Cyclone V GX Starter Kit: C5G_V.1.1.0_SystemCD/Demonstrations/C5G_LPDDR2_Nios_Test

Is there a setting that I need to change? I have tried to set the `default_nettype to "wire" but that doesn't seem to have an effect.

John

↧

Quartus 13.1,Qsys Generation Error only with PLL

April 4, 2014, 7:56 am

≫ Next: Debugging from memory and reset vector selection

≪ Previous: Compile errors with Qsys generated verilog

Hi,

i am using Quartus Version 13.1 and i cannot instantiate a PLL anymore.
When i try in Qsys i get the following error:

Code:

Error: 

    while executing

"__altera__safe_load C:/altera/13.1/quartus/bin/qcl_pll_tcl.dll generic_pll"

    ("uplevel" body line 1)

    invoked from within

"uplevel 1 

[list __altera__safe_load {*}$args]"

    (procedure "load" line 2)

    invoked from within

"load [file join $::quartus(binpath) qcl_pll_tcl.dll] generic_pll"

    ("windows" arm line 2)

    invoked from within

"switch $tcl_platform(platform) {

        windows {

            load [file join $::quartus(binpath) qcl_pll_tcl.dll] generic_pll

        }

        unix {

            load [file join $::qu..."

    ("package ifneeded ::altera::generic_pll 1.0" script)

    invoked from within

"package require ::altera::generic_pll"

Error: An instance of Altera PLL could not be created.

The component had an unexpected internal error.

In Quartus the MegaWirazd shows the blue loading module window but then just disappears.
Is it possible that i have a corrupt pll design file in my system? Or is there something else wrong?

Regards
Tim

↧

Debugging from memory and reset vector selection

April 4, 2014, 8:35 am

≫ Next: De2 gpio led circuit

≪ Previous: Quartus 13.1,Qsys Generation Error only with PLL

What is the guideline for setting the cpu reset vector when debugging using direct memory load (Eclipse Debug As Nios Hardware)? Does it vary based on specific target hardware / generation?

My standard procedure was to build a SOPC/QSYS system with reset vector pointing to RAM, debug the application, then rebuild the system and application with the reset vector pointing to the serial flash controller (or whatever flash device), and flash it. Not optimal, since you're not debugging the final .sof

Then I found that with a new design (Stratix V w/ EPCQ) that I could successfully load memory and debug without changing the reset vector temporily to RAM. (i.e reset vector is always in the final desired location)

So now I'm confused about when the sub-optimal debug method is required.

For my current project (DE0-Nano w/ Cyclone IV & EPCS) debug works fine if the reset vector points to RAM.
With the CPU reset vector set to the EPCS controller I'm getting a ELF verify failure ("Downloading ELF Process failed") in the EPCS controller section.

What's the full story, and where is it best documented?

↧

De2 gpio led circuit

April 4, 2014, 12:56 pm

≫ Next: Can't run DS-5 in 13.1

≪ Previous: Debugging from memory and reset vector selection

Hi,

I wanted make a simple LED circuit that would be powered by one of the gpio pins. I wanted to know how much current does each pin provide and would I need to use a transistor?

↧

Can't run DS-5 in 13.1

April 4, 2014, 12:56 pm

≫ Next: Can't run DS-5 in 13.1

≪ Previous: De2 gpio led circuit

This should be an easy fix, but...

I'm trying to upgrade to 13.1 of the EDS tools. After install, I open the Embedded Command Shell as usual, but when I type eclipse to launch DS-5, it throws an error which points me to the error log file. The log file contains this message:

!SESSION Fri Apr 04 13:35:50 MDT 2014 ------------------------------------------
!ENTRY org.eclipse.equinox.launcher 4 0 2014-04-04 13:35:50.283
!MESSAGE Could not find extension: reference:file:org.eclipse.osgi.nl_ja_3.7.0.v20110 723043401.jar
!ENTRY org.eclipse.equinox.launcher 4 0 2014-04-04 13:35:50.285
!MESSAGE Could not find extension: reference:file:org.eclipse.osgi.services.nl_ja_3.7 .0.v20110723043401.jar
!ENTRY org.eclipse.equinox.launcher 4 0 2014-04-04 13:35:50.285
!MESSAGE Could not find extension: reference:file:org.eclipse.osgi.util.nl_ja_3.7.0.v 20110723043401.jar
!ENTRY org.eclipse.equinox.launcher 4 0 2014-04-04 13:35:50.321
!MESSAGE Exception launching the Eclipse Platform:
!STACK
java.lang.ClassNotFoundException: org.eclipse.core.runtime.adaptor.EclipseStarter
at java.net.URLClassLoader$1.run(URLClassLoader.java: 202)
at java.security.AccessController.doPrivileged(Native Method)
at java.net.URLClassLoader.findClass(URLClassLoader.j ava:190)
at java.lang.ClassLoader.loadClass(ClassLoader.java:3 06)
at java.lang.ClassLoader.loadClass(ClassLoader.java:2 47)
at org.eclipse.equinox.launcher.Main.invokeFramework( Main.java:619)
at org.eclipse.equinox.launcher.Main.basicRun(Main.ja va:577)
at org.eclipse.equinox.launcher.Main.run(Main.java:14 10)
at com.arm.workbench.Hook.run(Hook.java:463)

I've tried uninstalling, rebooting my PC and re-installing, but still get this error. It looks like I'm missing some jar files, but I thought they would have been installed with the install executable. I didn't see this problem with 13.0sp1.

Any ideas?

↧