Hi, I am looking for a copy of max plus II 9.01 is there any where official I can download it from?
↧
Maxplus II download required 9.01
↧
Quartus Response Speed
Hi All,
I've noticed that when working with Quartus, at times it will slow down its response speed, and saving a file or project can go from nearly instantaneous to take well over 30 seconds. Compilation start time, the time that it takes between telling the program to compile and when it actually starts, can take up to 5 minutes to begin. I try deleting the db and incremental_db, but this seems to have no effect. Any thoughts on what could be causing this slowdown?
I've noticed that when working with Quartus, at times it will slow down its response speed, and saving a file or project can go from nearly instantaneous to take well over 30 seconds. Compilation start time, the time that it takes between telling the program to compile and when it actually starts, can take up to 5 minutes to begin. I try deleting the db and incremental_db, but this seems to have no effect. Any thoughts on what could be causing this slowdown?
↧
↧
Mixing VHDL and Verilog
I have the Terasic Cyclone V board. They generate a Verilog top module with the board signal names that connect to the pins.
I have a VHDL file that instantiates this Verilog top module to get access to the board signals. However, when I program
the board my VHDL doesn't work.
I created a VHDL file with the board signal names and got rid of the Verilog file. That works.
How come my VHDL code did not work when Verilog was the top file with the board signal names?
I have a VHDL file that instantiates this Verilog top module to get access to the board signals. However, when I program
the board my VHDL doesn't work.
I created a VHDL file with the board signal names and got rid of the Verilog file. That works.
How come my VHDL code did not work when Verilog was the top file with the board signal names?
↧
Two processors with onchip memory
Hi,
I am developing a project with two processors and I'm just trying to send data from pc to master cpu through uart and then from master send that data to slave cpu and then back to pc though the uart. Do I need two different systems within quartus, should I be using subsystems, or would one system be functional with two cpu's and onchip-memory? Basically one processor should read and the other write. How can I do this without a mutex core. I've tried multiple methods without success.
Any help is appreciated.
I am developing a project with two processors and I'm just trying to send data from pc to master cpu through uart and then from master send that data to slave cpu and then back to pc though the uart. Do I need two different systems within quartus, should I be using subsystems, or would one system be functional with two cpu's and onchip-memory? Basically one processor should read and the other write. How can I do this without a mutex core. I've tried multiple methods without success.
Any help is appreciated.
↧
Cyclone IV Transciever Starter Kit
I am yet to be successful to commit NIOS II software to Flash.
I plan to use the "Update Portal" method since that works fine for the FPGA code .
I have the following to generate my nios_flash_sw.flash file.
elf2flash --base=0x01000000 --end=0x01ffffff --reset=0x01800000 --input=Cyclone_Led.elf --output=nios_flash_sw.flash --boot=./boot_loader_cfi.srec
The onlly problem is I can't see how the boot_loader code would know there the SSRAM resides inorder to do the initial FLASG -> SSRAM copy..
I would guess it is in the elf, but that means the .elf is the one that was run out of SSRAM initially. Is that correct ?
I set the NIOS II in QSYS to have a reset vector from the FLASH memory with an offset of 0x00800000 which is the offse tin FLASH where the User SW resides.and corresponds to the reset parameter for elf2flash cmd.
Best Regards, Bob.
I plan to use the "Update Portal" method since that works fine for the FPGA code .
I have the following to generate my nios_flash_sw.flash file.
elf2flash --base=0x01000000 --end=0x01ffffff --reset=0x01800000 --input=Cyclone_Led.elf --output=nios_flash_sw.flash --boot=./boot_loader_cfi.srec
The onlly problem is I can't see how the boot_loader code would know there the SSRAM resides inorder to do the initial FLASG -> SSRAM copy..
I would guess it is in the elf, but that means the .elf is the one that was run out of SSRAM initially. Is that correct ?
I set the NIOS II in QSYS to have a reset vector from the FLASH memory with an offset of 0x00800000 which is the offse tin FLASH where the User SW resides.and corresponds to the reset parameter for elf2flash cmd.
Best Regards, Bob.
↧
↧
Failed to read UART with non blocking mode
Hi
I am working with Altera FPGA DE2 with with Nios II 13.0sp1 Software Build Tools for Eclipse, first I worked with UART with blocking mode using open(), read() and write() functions, It worked fine, but when I change to non blocking mode (I added O_NONOBLOCK to the open function), but the read call fails, it returns -1, and then I read the errno value and it was 12 which corresponds to ENOMEM. I have found a similar post but it was not answered. Is that a way to fix this ?
Any idea or comment is welcomed
Thank you in advance
I am working with Altera FPGA DE2 with with Nios II 13.0sp1 Software Build Tools for Eclipse, first I worked with UART with blocking mode using open(), read() and write() functions, It worked fine, but when I change to non blocking mode (I added O_NONOBLOCK to the open function), but the read call fails, it returns -1, and then I read the errno value and it was 12 which corresponds to ENOMEM. I have found a similar post but it was not answered. Is that a way to fix this ?
Any idea or comment is welcomed
Thank you in advance
↧
Baremetal?!!
By way of democracy ask to create forum "Baremetal", then I kill this message ! :)
↧
Does Quartus support using a VHDL configuration as a top-level entity?
The question title says it all. I thought it would be pretty straightforward to do so, since Quartus already handles most of the configuration capabilities of VHDL, and this should be possible as specified in the language standard.
Anyway, here is some source code that demonstrates the issue. The problem is that the code compiles ok if I specify logic_function as the top-level entity, but it gives the following error if I specify logic_function_cfg as the top-level entity:
Error (12007): Top-level design entity "logic_function_cfg" is undefined
Anyway, here is some source code that demonstrates the issue. The problem is that the code compiles ok if I specify logic_function as the top-level entity, but it gives the following error if I specify logic_function_cfg as the top-level entity:
Error (12007): Top-level design entity "logic_function_cfg" is undefined
Code:
----------------------------------------
entity nand_gate is
port (
a, b: in bit;
y: out bit
);
end;
architecture dataflow of nand_gate is
begin
y <= a nand b;
end;
----------------------------------------
entity xor_gate is
port (
a, b: in bit;
y: out bit
);
end;
architecture dataflow of xor_gate is
begin
y <= a xor b;
end;
----------------------------------------
entity logic_function is
port (
a, b: in bit;
y: out bit
);
end;
architecture dataflow of logic_function is
component gate_component is
port (
a, b: in bit;
y: out bit
);
end component;
begin
gate_instance: component gate_component
port map (a => a, b => b, y => y);
end;
----------------------------------------
configuration logic_function_cfg of logic_function is
for dataflow
for gate_instance: gate_component
use entity work.nand_gate;
end for;
end for;
end;
----------------------------------------↧
Cyclone V - Counter not counting correctly
Hi,
I don't know if this is the correct section for this issue since it could also be a VHDL problem, but because I think my source code is correct, I post it here.
My (serious) problem is that I use a counter that I declared as follows in my design to generate SPI "states" (clock, mosi bits, read miso data, etc . . . ) for an ADS1158 AD converter.
I use this signal as a "state counter" which I increment throughout a SPI data transfer cycle by using the following expression:
The "state_regsiter" signal is the expression in a case statement that looks like this:
This "state machine" counts up to 99 for a whole 3 Byte data read transfer from the ADS1158.
I use this kind of "state machine" because there are several "spots" during the data transfer where I would like to peek into the data already read from the ADS (like status and channel ID). Otherwise I would have implemented a "real" state machine where I would have defined some kind of state types.
Anyway, my problem is that, according to modelsim, this state counter works as expected: It increments by "1" after each current "state" is processed.
If I synthesize this with Quartus II V13.1 or 14.0, it happens from time to time that the counter does not increment by "1", but by a random number. I confirmed that by using Signal Tap II (see attachment). The signal tap screenshot shows a value of 33 right after 0 which in my opinion is not possible if one looks at the source code. I also observed other values like 64 or 65.
From this "little" error on, everything works as described in the vhdl code until the next error of this kind occurs. The errors occur randomly in time, but svereral times a second (I sample 8 differential channels of the ADC with 1kHz).
The design is fully timing constrained with a sdc file for my own QSYS components and the additional QSys generated sdc files. The timing reports show no errors or hints for this behaviour (I have to admit that I'm not a Timequest expert, though). The clock I use in this component is the h2f_user0_clk running at 100MHz. The FMax report of Timequest shows me that this clock can work up to 106MHz.
The case statement runs in a synchronized process (synchronized to this h2f_user0_clk).
I really don't understand what is going on here . . .
I use a simple counter in a fully constrained design and modelsim is telling me that the logic is correct. Why the hell do I experience this kind of counting error?
Any help is very much appreciated. I will also post additional informations about my design if requested.
Regards,
Maik
I don't know if this is the correct section for this issue since it could also be a VHDL problem, but because I think my source code is correct, I post it here.
My (serious) problem is that I use a counter that I declared as follows in my design to generate SPI "states" (clock, mosi bits, read miso data, etc . . . ) for an ADS1158 AD converter.
Code:
signal state_register : unsigned(7 downto 0) := (others => '0');I use this signal as a "state counter" which I increment throughout a SPI data transfer cycle by using the following expression:
Code:
state_register <= state_register + 1;Code:
case to_integer(state_register) is
when 0 => is_ads_n_cs <= '1'; -- IDLE State
is_spi_clk <= '0';
current_mosi_bit <= '0';
t_cssc_counter <= 0;
if(write_ads_registers = '1' or read_ads_registers = '1') then
is_ads_n_cs <= '0';
state_register <= state_register + 1;
elsif(read_ads_channel_data = '1' and
(ads_n_dready = '0' or (ads1158_component_status(1) = '1' and cyclic_processing_write_read_flag = '0')) and
kilo_sample_flag = '1' and
ads1158_component_status(0) = '0') then
if(ads1158_component_status(1) = '1' and cyclic_processing_write_read_flag = '0') then
ads_command_byte <= ADS_COMMAND_PULSE_CONVERT;
end if;
is_ads_n_cs <= '0';
state_register <= state_register + 1;
elsif(read_ads_channel_data = '1' and ads1158_component_status(0) = '1' and kilo_sample_flag = '1') then
state_register <= x"61";
end if;
when 1 => if(t_cssc_counter < 7) then
t_cssc_counter <= t_cssc_counter + 1;
if((write_ads_registers = '1' or read_ads_registers = '1') or ads1158_component_status(1) = '1') then
current_mosi_bit <= ads_command_byte(ads_data_byte_ptr); -- 7
end if;
else
state_register <= state_register + 1;
end if;
when 2 => is_spi_clk <= '1'; -- 1st rising edge of spi_sclk
read_status_byte(ads_data_byte_ptr) <= spi_miso;
state_register <= state_register + 1;
when 3 => ads_data_byte_ptr <= ads_data_byte_ptr - 1; -- 6
state_register <= state_register + 1;
when 4 => is_spi_clk <= '0'; -- 1st falling edge of spi_sclk
state_register <= state_register + 1;
when 5 => if((write_ads_registers = '1' or read_ads_registers = '1') or ads1158_component_status(1) = '1') then
current_mosi_bit <= ads_command_byte(ads_data_byte_ptr); -- 6
end if;
state_register <= state_register + 1;
......I use this kind of "state machine" because there are several "spots" during the data transfer where I would like to peek into the data already read from the ADS (like status and channel ID). Otherwise I would have implemented a "real" state machine where I would have defined some kind of state types.
Anyway, my problem is that, according to modelsim, this state counter works as expected: It increments by "1" after each current "state" is processed.
If I synthesize this with Quartus II V13.1 or 14.0, it happens from time to time that the counter does not increment by "1", but by a random number. I confirmed that by using Signal Tap II (see attachment). The signal tap screenshot shows a value of 33 right after 0 which in my opinion is not possible if one looks at the source code. I also observed other values like 64 or 65.
From this "little" error on, everything works as described in the vhdl code until the next error of this kind occurs. The errors occur randomly in time, but svereral times a second (I sample 8 differential channels of the ADC with 1kHz).
The design is fully timing constrained with a sdc file for my own QSYS components and the additional QSys generated sdc files. The timing reports show no errors or hints for this behaviour (I have to admit that I'm not a Timequest expert, though). The clock I use in this component is the h2f_user0_clk running at 100MHz. The FMax report of Timequest shows me that this clock can work up to 106MHz.
The case statement runs in a synchronized process (synchronized to this h2f_user0_clk).
I really don't understand what is going on here . . .
I use a simple counter in a fully constrained design and modelsim is telling me that the logic is correct. Why the hell do I experience this kind of counting error?
Any help is very much appreciated. I will also post additional informations about my design if requested.
Regards,
Maik
↧
↧
difference of nios II\e and nios II\f processor
Hi
I am new to NIOS II processor.wants to know the main difference of NIOS II\e and NIOS II\f processor and i wants to update the processor from
NIOS II\f to nios II\e. what will be the major changes it will effect. pls explain in detail.
I am new to NIOS II processor.wants to know the main difference of NIOS II\e and NIOS II\f processor and i wants to update the processor from
NIOS II\f to nios II\e. what will be the major changes it will effect. pls explain in detail.
↧
modelsim testbench problem
Hi,
I'm trying to simulate a system. Please find the attachement for the code.
Running the RTL simulation, I can't see in Modelsim the "i2c_slave_device" component.
Where am I wrong?
PS: I wrote the "i2c_slave_device" only for simulation purpose and it is not part of the "Channel_MNG" project.
Thanks for your help.
I'm trying to simulate a system. Please find the attachement for the code.
Running the RTL simulation, I can't see in Modelsim the "i2c_slave_device" component.
Where am I wrong?
PS: I wrote the "i2c_slave_device" only for simulation purpose and it is not part of the "Channel_MNG" project.
Thanks for your help.
↧
FPGA code program vhdl
A. I have two 6 bit numbers outputs(image and word comparison) in scale 32 which are the results of my program.How i can show one of the two 6 bit numbers in scale from 100(if this can't be done i can make the conversion) alternately( i mean every 2-3 seconds they will change to the other.For example first will show the image and after 2-3 seconds the word and after 2-3 seconds the image again) or I could use two switches and choose which comparison i would like to show.
B. Also it must show in the first display from the left the number of the choice for example 1 is for image comparison and 2 for the word comparison. The other 3 displays will show the number from scale of 100.(0-100)
In addition during the calculations of the two comparisons FPGA the 4 displays must show 0000 and after the calculations of the results has finished then they will do this i said before in A and B
Thank you.
B. Also it must show in the first display from the left the number of the choice for example 1 is for image comparison and 2 for the word comparison. The other 3 displays will show the number from scale of 100.(0-100)
In addition during the calculations of the two comparisons FPGA the 4 displays must show 0000 and after the calculations of the results has finished then they will do this i said before in A and B
Thank you.
↧
Installing Quartus II device files (.qdz) on Quartus II 13.1
Hi,
I'm trying to install device files for Quartus II 13.1 on Windows 7, but get the error "Can't find Quartus II Web Edition device files (.qdz) in directory ..." (see picture)
quartuserror.jpg
Did anyone else hit this Problem?
Gruß Tobi
I'm trying to install device files for Quartus II 13.1 on Windows 7, but get the error "Can't find Quartus II Web Edition device files (.qdz) in directory ..." (see picture)
quartuserror.jpg
Did anyone else hit this Problem?
Gruß Tobi
↧
↧
AltASMI megafunction status read is shifted right by one
I use Altera AltASMI megafunciont for EPCS64 device with Stratix2 GX FPGA.
My problem is When I read the Status register, I read status word shifted right by one.
I also had this problem when I used AltRemote megafunction and I read the status word. It was also shifted by one.
It's quite strange becasuse I can read the EPCS bytes correctly.
I have Quartus2 13.0 sp1.
Can anyone help please?
My problem is When I read the Status register, I read status word shifted right by one.
I also had this problem when I used AltRemote megafunction and I read the status word. It was also shifted by one.
It's quite strange becasuse I can read the EPCS bytes correctly.
I have Quartus2 13.0 sp1.
Can anyone help please?
↧
SynplifyPro for .vqm then Quartus P&R - Can't compile duplicate entity
I'm using Synplify Pro which compiles my .VHDL file and several Altera IP cores. The output is a .VQM.
This is then input to Quartus for P&R. All scripts. quartus_sh is passed a .tcl file.
It gives several errors: "Can't compile duplicate declarations of entity " ... " into library "work".
Anyone know what's wrong?
I have a similar project with just one IP core and that synthesized OK. Scripts are the same except
for the added QIP files.
Thanks
This is then input to Quartus for P&R. All scripts. quartus_sh is passed a .tcl file.
It gives several errors: "Can't compile duplicate declarations of entity " ... " into library "work".
Anyone know what's wrong?
I have a similar project with just one IP core and that synthesized OK. Scripts are the same except
for the added QIP files.
Thanks
↧
Quartus fitter does not optimize as expected
Hi,
I'm a seasoned ASIC designer but newbie in the FPGA field. Putting together a design, synthesis it and fit it a cyclone V went rather smooth but when I was looking at the result I thought it was a bit big. The design consist of many maximum operations like "X>Y ? X : Y" so i made a new design with only this operation to see what was happening. Reading Altera documentation I expected the tool to use arithmetic mode for the ALM and the number of ALM's to be ~10 when X,Y and R are 20 bits, this is however not the case. I tried several different coding styles but I never get below 20 ALM's and the subtraction and muxing are always put in separate ALM's although it should be possible to fit these in the same ALM (like they do in http://www.altera.com/literature/wp/wp-01035.pdf for the startix II device).
So my question is: have I misunderstood the arithmetic mode of the Cyclone V ALM or is their a way to get the optimized result which i expect and if so what do I need to do to get it. Below is one of the version of the max operations i tried.
module test
(input wire clk,
input wire rst_an,
input wire [19:0] X,
input wire [19:0] Y,
output reg [19:0] R
);
wire [19:0] max;
assign max = (X < Y) ? Y : X;
always @(posedge clk or negedge rst_an)
if (!rst_an)
R <= 20'b0;
else
R <= max;
endmodule
Best Regards
Mikael Korpi
I'm a seasoned ASIC designer but newbie in the FPGA field. Putting together a design, synthesis it and fit it a cyclone V went rather smooth but when I was looking at the result I thought it was a bit big. The design consist of many maximum operations like "X>Y ? X : Y" so i made a new design with only this operation to see what was happening. Reading Altera documentation I expected the tool to use arithmetic mode for the ALM and the number of ALM's to be ~10 when X,Y and R are 20 bits, this is however not the case. I tried several different coding styles but I never get below 20 ALM's and the subtraction and muxing are always put in separate ALM's although it should be possible to fit these in the same ALM (like they do in http://www.altera.com/literature/wp/wp-01035.pdf for the startix II device).
So my question is: have I misunderstood the arithmetic mode of the Cyclone V ALM or is their a way to get the optimized result which i expect and if so what do I need to do to get it. Below is one of the version of the max operations i tried.
module test
(input wire clk,
input wire rst_an,
input wire [19:0] X,
input wire [19:0] Y,
output reg [19:0] R
);
wire [19:0] max;
assign max = (X < Y) ? Y : X;
always @(posedge clk or negedge rst_an)
if (!rst_an)
R <= 20'b0;
else
R <= max;
endmodule
Best Regards
Mikael Korpi
↧
Stratix V Development board with QSFP ports
Hi,
We have just bought a Bittware S5-PCIe-HQ development board which has a Stratix V FPGA.
On the board are 2 QSFP+ ports. We wish to use these ports to transmit and receive data to and from the FPGA (probably using an Ethernet interface) but we don't know where to start.
I don't have too much of knowledge of FPGAs but if anyone has knowledge of this or can point me in the right direction it would be much appreciated.
Thanks,
Paul
We have just bought a Bittware S5-PCIe-HQ development board which has a Stratix V FPGA.
On the board are 2 QSFP+ ports. We wish to use these ports to transmit and receive data to and from the FPGA (probably using an Ethernet interface) but we don't know where to start.
I don't have too much of knowledge of FPGAs but if anyone has knowledge of this or can point me in the right direction it would be much appreciated.
Thanks,
Paul
↧
↧
Power Consumption Cyclone SXF - U23 vs F31 Package
Hi,
I have the Altera Cyclone V SoC Dev Board, with which I measure the power consumption of the FPGA and HPS.
Unfortunately for me the Cyclone V chip comes in the F31 package (896 pins). However, I want to know the power consumption of the U23 package (672 pins), which I will be using for my board.
Do you guys know if the U23 package with fewer pins has the same power consumption or less than that?
Cheers,
Adam
I have the Altera Cyclone V SoC Dev Board, with which I measure the power consumption of the FPGA and HPS.
Unfortunately for me the Cyclone V chip comes in the F31 package (896 pins). However, I want to know the power consumption of the U23 package (672 pins), which I will be using for my board.
Do you guys know if the U23 package with fewer pins has the same power consumption or less than that?
Cheers,
Adam
↧
A Question About Constraints
I understand the clock constraining.
But what about the non-clock signals.
For example, I have a small VHDL design (1 file) that has a several clocks,
a reset, and some LED output signals. The constraint file was generated by
the Terasic people that made the board. When synthesized the results show
the design is NOT constrained. When you look at the constraint file
the reset and LED signals are not in there. When running the Timing Analyzer
it shows the reset and LEDs as unconstrained.
What do you do with them? What constraint, if any do you use? There's very
little literature about this at least I can't find any.
In the past I have usually had them as Set Input Delay constrained to the period
of the clock. Probably has no affect.
Thanks
PWS
But what about the non-clock signals.
For example, I have a small VHDL design (1 file) that has a several clocks,
a reset, and some LED output signals. The constraint file was generated by
the Terasic people that made the board. When synthesized the results show
the design is NOT constrained. When you look at the constraint file
the reset and LED signals are not in there. When running the Timing Analyzer
it shows the reset and LEDs as unconstrained.
What do you do with them? What constraint, if any do you use? There's very
little literature about this at least I can't find any.
In the past I have usually had them as Set Input Delay constrained to the period
of the clock. Probably has no affect.
Thanks
PWS
↧
Synplify Pro Cyclone V Part Numbers
Using Synplify Pro as a synthesis tool we pass it a project file that has all of the
options and input files. One such option is the following which is wrong.
set_option -technology CYCLONE V
set_option -part 5CGX etc
Does anyone know where the correct numbers are for the -part Cyclone series chips
are?
For example, I had a Cyclone II and it took me 30 minutes or so to finally get the number
correct. I was using the full part number and Synplify did not like that. Below is
what it likes.
The correct format for this is:
set_option -technology CYCLONEII
set_option -part EP2C70
There must be a list somewhere. A search on the internet did not provide me with any answers.
Also, is there a space after the word CYCLONE before one puts a II or V ?
There was no space above and it worked. There must some document describing
the correct syntax. I have not found it.
Thanks,
PWS
options and input files. One such option is the following which is wrong.
set_option -technology CYCLONE V
set_option -part 5CGX etc
Does anyone know where the correct numbers are for the -part Cyclone series chips
are?
For example, I had a Cyclone II and it took me 30 minutes or so to finally get the number
correct. I was using the full part number and Synplify did not like that. Below is
what it likes.
The correct format for this is:
set_option -technology CYCLONEII
set_option -part EP2C70
There must be a list somewhere. A search on the internet did not provide me with any answers.
Also, is there a space after the word CYCLONE before one puts a II or V ?
There was no space above and it worked. There must some document describing
the correct syntax. I have not found it.
Thanks,
PWS
↧