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Cyclone V: FPGA and HPS in JTAG chain - SFL loader error

October 20, 2014, 12:21 am
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Self-made board with 5CSEMA5F31I7N. Windows 7 x64, Quartus 13.1 and Quartus 14.0

Without HPS in JTAG chain (5CSEMA5F31I7N with JTAG chain: header pin 9 to FPGA_TDI; FPGA_TDO to header pin 3) works properly:
Auto detect show me 5CSEMA5;
Attach flash devices -> EPCQ128
Add file: LED_Blink.jic; Program.
Result: EPCQ128 programmed, FPGA after power-on loaded and LED blinked without connected JTAG.

Problem: both FPGA and HPS in JTAG chain
5CSEMA5F31I7N with JTAG chain: header pin 9 to FPGA_TDI; FPGA_TDO to HPS_TDI; HPS_TDI to header pin 3.
Auto detect show me FPGA and HPS in JTAG chain;
LED_Blink.sof programming works properly – LED blinking.
Next step:
Attach flash devices -> EPCQ128
Add file: LED_Blink.jic (used in JTAG chain without HPS)
I see serial flash loader programming problem:
Error(209015): Can't configure device. Expected JTAG ID code 0x02D120DD for device1, but found JTAG ID code 0xFFFFFFFF.
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MAX2 alternative to XC95144XL

October 20, 2014, 4:19 am
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Dear All,

I am interested in the MAX2 cpld family to replace a Xilinx XC95144XL part to be used in 3V3 circuit. I am thinking in the EPM570 part. In terms of resources available in this part, can I make a direct comparison between the two parts? For instance the Macrocells number can be directely compared between these two parts?

Best regards,
Oscar
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i need help, i want to use triple speed ethernet ip.

October 20, 2014, 5:47 am
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i use quartus II 12.1 sp , Cyclone IV EP4CGX110DF31I7N.
i want to use Triple speed ethernet. bu but compile error.
29219Core "Triple Speed Ethernet" (6AEF7_00BD) is not enabled for current device family.
10003 Can't open ecrypted VHDL or VeilogHDL file "D:/Work/.../sumodules/altera_tse_a_fifo_13.v"--current license file does not contain a vailed license for encrypted file

how can i solve this problem?
and Why Cyclone IV EP4CE115F29C7N is can compile?
please, help me.
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11802 can't fit design in device.

October 20, 2014, 7:20 am
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Hello im using quartus 13.1 and I installed "a" patch. But still I get the can't fit design in device error.
And this is the getting started build.

I tried updating to version 14 but in doing so I have more problems.
How do I get v13.1 to work on cyclone 5 board??
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Quartus II Unexpected Simulation Of Clock Outputs

October 20, 2014, 8:16 am
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I have recently had to pick up an old Quartus II V5 project (schematics) from 2005 but have not done any logic design since then. Not wishing to encounter too steep a learning curve, I have installed Quartus II V9.1 SP2 Web Edition principally because I wanted to continue with the Altera simulator.
I have made the changes to the designs and been going through the verification process of simulation using some of the original project .vwf files. Everything was going well until I noticed some strange behaviour on a couple of outputs.
The device is a MAXII EPM2210 and the design includes a totally stand alone dual clock generator function which runs from a 7.5MHz input pin. This Clock input is fed directly to one output pin and via an inverter to another pin. External to the device, these two output signals are then routed back into the two Global Clock input pins.
What I have found recently is that the two clock output signals are not always coming out as 7.5Mhz during simulation. The output waveforms are not consistent in frequency but are always the invertion of each other.
I have reduced the simulation to include just these five signals and found that by simply changing the start position of the master input clock signal, the shape of the two clock outputs will be affected and eventually be square at 7.5MHz. Also, if I remove the two global clock inputs from the simulation, the outputs are good.
I have tried both Timing and Functional simulation and tried forcing LCELL use to extend delays which have not cleared the problem.
So Quartus seems adamant that there is a problem but I cannot help but feel this is a quirk somewhere in the IDE.
There are no warnings anywhere relating to this part of the project design.
Anybody seen this kind of thing before or got any ideas as to what could be causing this?
Thanks.

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Unable to update property "Weak Pull-Up Resistor"

October 20, 2014, 12:29 pm
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Hi,

I am trying to set assign an internal pull up resistor to an input on the Cyclone IV E: EP4CE15F23C8 on Quartus II 11.0. I have tried using both the assignment editor and the pin planner to accomplish this, but after compilation this critical error always appears: Critical Warning: Unable to update property "Weak Pull-Up Resistor" of node "iDestuffed". The pin I am trying to assign is pin L6, I have tried some other pins and most also experience the same problem, but pin K1 does not. I can't seem to find the difference between the two pins. Is there some way to remedy this or another way to pull up the signal.

Thanks in advance.
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Open wav file in nios Eclipse

October 20, 2014, 12:34 pm
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HI

I made an SOPC and I can load a sound to line out in kit DE2. But I want to load a wave file to the audio codec.
I use the function :
File *fp;
fp = fopen(wav_file,"rb");
if (fp==NULL)
printf("Error: cannot open file \n");
to open wave file. Some wave files i addded to project and the path and file name i defined. But i didn't work.

What problem i have made?
:confused::(
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Channel in global memory

October 20, 2014, 2:47 pm
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Is it possible to create a channel in global (off-chip) memory?
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Using Modelsim SPD file

October 20, 2014, 3:33 pm
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I'm trying to perform some simulations using Modelsim. When I set up the new configuration I get an error saying "SEVERE: The specified Qsys Testbench Simulation Package Descriptor (.spd) file does not exist." How do you generate the .spd file?
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modelsim timing simulation error

October 20, 2014, 7:32 pm
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i did some timing simulation with quartus 13.0 modelsim, and it gave me errors. but the functional sim is all right.

the transcript content:

# do EXP02.do
# ** Warning: (vlib-34) Library already exists at "work".
#
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module EXP02
#
# Top level modules:
# EXP02
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
# -- Compiling module EXP02_vlg_sample_tst
# -- Compiling module EXP02_vlg_check_tst
# -- Compiling module EXP02_vlg_vec_tst
#
# Top level modules:
# EXP02_vlg_vec_tst
# vsim -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L max_ver -c -t 1ps -novopt work.EXP02_vlg_vec_tst
# Loading XXXXXXXXX
........
# Loading work.EXP02_vlg_check_tst
# ** Error: EXP02_v.sdo_typ.csd: syntax error, unexpected $end, expecting '('
# ** Error: (vsim-SDF-3445) Failed to parse SDF file "EXP02_v.sdo".
# Time: 0 ps Iteration: 0 Instance: /EXP02_vlg_vec_tst File: EXP02.vt
# Error loading design
Attached Images
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VHDL design for 8 bit shift register

October 20, 2014, 10:28 pm
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I need to program an 8 bit shift register, which will be used in a 4-bit multiplier.
Basically, this is what it should do:
1.- Receive inputs x (multiplier), sum (this comes from the adder segment of the multiplier), done, ad, sh, load
2.- WHen it receives the load signal, it must take the input values x
3.- when it gets the done signal, it must stop working
4.- when it gets the ad signal, it must replace the last 4 bits with the sum, also, when it gets sh it must shift

However, I don't seem to get the expected results. This is the code:

Code:
LIBRARY IEEE;USE ieee.std_logic_1164.all;


Entity registro8 IS
    PORT (load, sh, ad, Clock, done, z : IN  STD_logic;
            x,sum  : IN  STD_logic_vector (3 downto 0);
            m : OUT STD_logic;
            w : OUT STD_logic_vector(7 downto 0));
END registro8;


architecture reg of registro8 IS
signal s : std_logic_vector (7 downto 0);
begin
        process (load, x, sum, clock, sh, done, ad)
            begin
            if(done = '0') THEN
                if (load = '1') THEN
                    for i in 4 to 7 loop
                    s(i) <= x(i-4);
                    end loop;
                    for i in 0 to 3 loop
                    s(i) <= '0';
                    end loop;
                elsif (clock'event and clock = '1') THEN
                    if (ad = '1') THEN
                        for i in 0 to 3 loop
                        s(i) <= sum(3-i);
                        end loop;
                    elsif (sh = '1') THEN
                    s <= s(6 downto 0) & z;
                    END IF;
                end if;
                m <= s(7);
                w <= s;
            end if;
        end process;
end reg;
The main problem is that, after loading, the register seems to be deleted. Also, it continues to work, even if the done signal is 1.

Thanks for the help
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to use altlvds,how I can use LVDS bit clock and LVDS frame clock of ADC at the same t

October 20, 2014, 10:59 pm
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In my board, there are 5AGXFB3H4F40C5N and TI ADS5294.
The ADS5294 is a 80-MSPS 8-Channel ADC,The digital data from each channel ADC is output over two wires of LVDS output lines depending on the ADC sampling rate.The transmission signals between ADS5294 and FPGA are mainly LVDS bit clock ,LVDS frame clock and sampling data lines.
The ADC sampling rate is 80MSPS,
data rate of each data line is 560MSPS,
the frequency of LVDS bit clock is 280MHZ(DDR timing),
the frequency of LVDS frame clock is 40MHZ.
I want to receive sampling data with altlvds ip in FPGA, however,the altlvds ip only supply one clock input port.
My problem is ,to use altlvds,how I can use LVDS bit clock and LVDS frame clock of ADC at the same time ?
Attached Images
Attached Files
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PS2-Keyboard with Verilog...

October 21, 2014, 1:23 am
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Hello,here is one Keyboard for Verilog...

Code:
module keyboard (
  input clock,
  input ps2_data,
  input ps2_clk,
  output reg [7:0] led_g
);


parameter idle    = 2'b01;
parameter receive = 2'b10;
parameter ready  = 2'b11;


reg [1:0]  state=idle;
reg [15:0] rxtimeout=16'b0000000000000000;
reg [10:0] rxregister=11'b11111111111;
reg [1:0]  datasr=2'b11;
reg [1:0]  clksr=2'b11;
reg [7:0]  rxdata;


reg datafetched;
reg rxactive;
reg dataready;


always @(posedge clock )
begin
  if(datafetched==1)
    led_g <=rxdata;
end 
 
always @(posedge clock )
begin
  rxtimeout<=rxtimeout+1;
  datasr <= {datasr[0],ps2_data};
  clksr  <= {clksr[0],ps2_clk};


  if(clksr==2'b10)
    rxregister<= {datasr[1],rxregister[10:1]};


  case (state)
    idle:
    begin
      rxregister <=11'b11111111111;
      rxactive  <=0;
      dataready  <=0;
      rxtimeout  <=16'b0000000000000000;
      if(datasr[1]==0 && clksr[1]==1)
      begin
        state<=receive;
        rxactive<=1;
      end 
    end
   
    receive:
    begin
      if(rxtimeout==50000)
        state<=idle;
      else if(rxregister[0]==0)
      begin
        dataready<=1;
        rxdata<=rxregister[8:1];
        state<=ready;
        datafetched<=1;
      end
    end
   
    ready:
    begin
      if(datafetched==1)
      begin
        state    <=idle;
        dataready <=0;
        rxactive  <=0;
      end 
    end 
  endcase
end
endmodule
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MAXV - User Flash Memory Time Constraints

October 21, 2014, 4:40 am
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Hello,

I try to time constrain my design using Altera block ALTUFM_SPI. I get many warnings from Quartus software like this one:

Warning (332009): The launch and latch times for the relationship between source clock: clk_dsp_dpi_p4 and destination clock: inst54|auto_generated|maxii_ufm_block1|osc are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.

I cannot succeed to get rid of those warnings.

Would someone have an example (more likely an SDC file example) on how to constrain ALTUFM_SPI?

Thank you in advance for your comments.

Fabe
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Xilinx 8.1 & Xilinx 14.7 Version will not compile my design

October 21, 2014, 5:43 am
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Hi.

I designed the processor DorQ which is attached. It compiles fine in Quartus 2 but my business partners use Xilinx 8.1 & Xilinx 14.7 Version and on these software, it shows errors which are also attached to this thread.
Could someone please provide a solution to this problem. Is there a setting we can change on Xilinx 8.1 & Xilinx 14.7 Version that will do away with the error messages.
Thanks for your reply.
Attached Files
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Transceiver placement issue

October 21, 2014, 12:12 pm
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Is there any guru who can help to place more than one transceivers in one GXB block?
I tried to design two 2 channel transceivers in one GXB block that has 4 channels. Quartus II fitter always fails to place them with following error message,

Error (167005): Can't assign I/O pad "gxb_tx6" to PIN_H4 because this causes failure in the placement of the other atoms in its associated channel
Error (167009): Quartus II software cannot combine the following GXB Central control unit(s) due to inconsistent parameters and/or input connections
Error (21087): Input port "DPRIOIN" must be driven by the same source
Info (21090): Atom "cyclone4gx_2ch:inst1|c4gx_2ch:c4gx_2ch_inst|c4gx_ 2ch_alt_c3gxb:c4gx_2ch_alt_c3gxb_component|cent_un it0" is driven by source "cyclone4gx_2ch:inst1|altgx_reconfig:altgx_reconfi g_inst|altgx_reconfig_alt_c3gxb_reconfig_1801:altg x_reconfig_alt_c3gxb_reconfig_1801_component|altgx _reconfig_alt_dprio_v5k:dprio|dprioin~1"
Info (21090): Atom "cyclone4gx_2ch:inst2|c4gx_2ch:c4gx_2ch_inst|c4gx_ 2ch_alt_c3gxb:c4gx_2ch_alt_c3gxb_component|cent_un it0" is driven by source "cyclone4gx_2ch:inst2|altgx_reconfig:altgx_reconfi g_inst|altgx_reconfig_alt_c3gxb_reconfig_1801:altg x_reconfig_alt_c3gxb_reconfig_1801_component|altgx _reconfig_alt_dprio_v5k:dprio|dprioin~1"

it looks like i violate the law that only one reconfig instance could be designed for one block. But when removed one it still says error. and here is the message,

Critical Warning (167080): GXB Central Management Unit (CMU) cyclone4gx_2ch:inst|c4gx_2ch_nb:c4gx_2ch_nb_inst|c 4gx_2ch_nb_alt_c3gxb:c4gx_2ch_nb_alt_c3gxb_compone nt|cent_unit0 is not connected to a GXB reconfig logic block, but the RX offset cancellation feature requires that it must be

Is there any design example which places more than one independent transceiver in one GXB block?

Appreciated!

Yaoting
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if

October 21, 2014, 12:43 pm
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pressBoth : process(b0,b1)
variable resetslv: std_logic_vector(3 downto 0);

begin
if ((b0 ="0000") and (b1 ="0000")) then <<<<* This is line 85*
counter0 <='0';
counter1 <='0';
end if;
resetslv := std_logic_vector(counter1 and counter0);
sseg2 <= ssegCode(resetslv);

end process;

Im getting the error : Error (10327): VHDL error at buttons.vhd(85): can't determine definition of operator ""="" -- found 0 possible definitions

i basically want to press two buttons b0 and b1 and when they are both pressed for the counters to be reset back to 0, i already have each button incrementing seperately.
Not sure what's going on here .. Any help appreciated.
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USB Camera Not Detected

October 21, 2014, 2:45 pm
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Hi there,

I am using the DE1-SoC with the Linux distribution from the terasic site and am trying to view a camera feed from a USB camera. I have a Logitech C200, which should work out of the box since it uses UVC drivers. I tried bringing up Cheese to view the feed, but it says there is no device! I think it is because there actually is no UVC driver (since the distro is based on Linaro). Can anyone confirm that this is the problem and how to fix it? I just want to use a webcam!

Thanks,
Mike
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SoCKit JTAG PROGRAMMING problem: -- expected 1 device(s) but found 2 device(s)

October 21, 2014, 2:53 pm
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Hi. Did "my_first_fpga" and "my_first_HPS" with SoCKit -- no problems. Now, I can no longer program the fpga on Cyclone V. Programmer gives error "209031 Device chain in Chain Description File does not match physical device chain -- expected 1 device(s) but found 2 devices(s)". Windows Device Manager reports 2 drivers under JTAG cables, (1) Altera USB-Blaster II (JTAG interface) and (2) Altera USB-Blaster II (System Console Interface). Pls help - thx.
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How to edit the current ip from ip catalog

October 21, 2014, 5:23 pm
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Hi,
I just upgraded my Quartus II rev13.0 to rev14.0. I found this time MegaWizard Plug-in Manager is gone but we have a new animal "IP-catalog".
IP-catalog can help me to generate a new ip just as the same as the old MegaWizard did. But, i did not find Edit function as MegaWizad did. Only we have is "Add" button.
Is there any one who can advise me how to edit my current IP design by using IP catalog instead of redoing a new one?

Thanks

Yaoting
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