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JTAG prgramming is not working in my Cyclone 4 based board.

December 27, 2014, 10:23 pm
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Hi all,
I'm new to this forum. I have one issue in my Cyclone 4 (EP4CE6E22C8N) based development board..
Please provide some basic tips.

FYI: TDI, TMS pins of the JTAG connector always LOW (even I have pulled up by 10K resistor), I belive, it should not be LOW..


Please share your solution .

Thanks in advance..
ABCD
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Stratix IV GX : Recovering the preloaded jic

December 28, 2014, 7:34 am
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Hi all,

I have erased the preloaded jic from Stratix IV GX development board. Is there a way to reload it? Where can find the jic?
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Error: top level design entity "adc_system" is undefined / Pin Assignment for ADC

December 28, 2014, 11:31 am
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Hello everybody!!!

Is it that there's an error in the Tutorial "Using the DE0-Nano ADC Controller"?

Using the code on page 10, starting Analysis & Synthesis results in the error "top level design entity "adc_system" is undefined".

First line of code is: module adc_demo... Using adc_system instead seems to work.


How are the pins assigned? -> Attachment


Cheers
Attached Images
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Difference among Qsys Sim model, test-bench Qsys sys and test-bench Sim model

December 28, 2014, 3:11 pm
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I'm confused about the purposes of different models that are offered during the generation process. In 'Generation' window you can have:
1) Simulation model
2) Test-bench Qsys system
3) Test-bench simulation model
4) Synthesis files (which I understand its purpose)

My understanding is that (2) is a wrapper system that contains the Qsys system to be tested, it also contains BFMs that are connected to the top-level interfaces of the system to be tested. By writing another HDL file that drives the top-level interfaces, I can check the behaviour of the system.

Q1: If the above is correct, now I want to do that in ModelSim, my guess is that having (2) alone is not enough, I also need (3) so that (2) can be simulated in ModelSim, is that correct?

Q2: If my guess in Q1 is correct, then in what situation I may want to generate (2) alone without generating (3)? (I think this is explained in "Qsys System Design Tutorial" but I didn't quite follow it..)

Q3: Is (1) a subset of (2)+(3)? My understanding is that (2)+(3) = (1)+(BFMs simulation model), is that correct?

Q4: If I just want to test/simulate my Qsys system using standard BFMs in ModelSim, it is OK to unclick (1) and only use (2)+(3), is that correct?
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error in pin planner

December 28, 2014, 8:19 pm
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hello all,

i got one error in pin planner that is Error (176172): Can't place node "hsync_n" -- node is a differential I/O node.

with this post i am attached .Qsf file. i dont know why this error comes and how to resolve it.
i also check 'IO_MAXIMUM_TOGGLE_RATE "0MHz"' settings that was not removed. so plz give me some solution about this error.
Attached Files
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can i read 2 input analog in DE0 nano without switch selector???

December 28, 2014, 8:51 pm
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i read the manual book that explain DE0 nano have IC ADC to read analog data but it's just can access 1 pin in one time using a switch selector, then i read the program demo on deo nano sample itls using pin from switch selector can i read without switch selector (in program below)???. i try to change with biner value but nothing effect it's just read input with pin selector switch that selected, did someone experience read the analog in DE0 Nano like this can you help me ???



Program ADC_control demo

module ADC_CTRL (
iRST,
iCLK,
iCLK_n,
iGO,
iCH,
oLED,

oDIN,
oCS_n,
oSCLK,
iDOUT
);

input iRST;
input iCLK;
input iCLK_n;
input iGO;
input [2:0] iCH;
output [7:0] oLED;

output oDIN;
output oCS_n;
output oSCLK;
input iDOUT;

reg data;
reg go_en;
wire [2:0] ch_sel;
reg sclk;
reg [3:0] cont;
reg [3:0] m_cont;
reg [11:0] adc_data;
reg [11:0] nilaiadc;
reg [7:0] led;

assign oCS_n = ~go_en;
assign oSCLK = (go_en)? iCLK:1;
assign oDIN = data;
assign ch_sel = iCH;
assign oLED = led;

always@(posedge iGO or negedge iRST)
begin
if(!iRST)
go_en <= 0;
else
begin
if(iGO)
go_en <= 1;
end
end

always@(posedge iCLK or negedge go_en)
begin
if(!go_en)
cont <= 0;
else
begin
if(iCLK)
cont <= cont + 1;
end
end

always@(posedge iCLK_n)
begin
if(iCLK_n)
m_cont <= cont;
end

always@(posedge iCLK_n or negedge go_en)
begin
if(!go_en)
data <= 0;
else
begin
if(iCLK_n)
begin
if (cont == 2)

data <= iCH[2]; //selektor switch

else if (cont == 3)

data <= iCH[1]; //selektor switch

else if (cont == 4)

data <= iCH[0];//selektor switch

else
data <= 0;
end
end
end

always@(posedge iCLK or negedge go_en)
begin
if(!go_en)
begin
adc_data <= 0;
led <= 8'h00;
end
else
begin
if(iCLK)
begin
if (m_cont == 4)
adc_data[11] <= iDOUT;
else if (m_cont == 5)
adc_data[10] <= iDOUT;
else if (m_cont == 6)
adc_data[9] <= iDOUT;
else if (m_cont == 7)
adc_data[8] <= iDOUT;
else if (m_cont == 8)
adc_data[7] <= iDOUT;
else if (m_cont == 9)
adc_data[6] <= iDOUT;
else if (m_cont == 10)
adc_data[5] <= iDOUT;
else if (m_cont == 11)
adc_data[4] <= iDOUT;
else if (m_cont == 12)
adc_data[3] <= iDOUT;
else if (m_cont == 13)
adc_data[2] <= iDOUT;
else if (m_cont == 14)
adc_data[1] <= iDOUT;
else if (m_cont == 15)
adc_data[0] <= iDOUT;
else if (m_cont == 1)
nilaiadc <= adc_data[11:4];
end

end

endmodule
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VIP core simulation error

December 28, 2014, 10:59 pm
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hi, everyone.

I am trying to simulate VIP-IP core.
when I tried to simulate the core with Qsys model-sim gave me some errors those are like.


.../db/ip/camCore/camCore.v(32): Module parameter 'AUTO_CONTROL_CLOCKS_SAME' not found for override.

I can not touch inside of it core, how can I solve that problem?
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I cannot generate .sof file

December 29, 2014, 3:32 am
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Hi! i create a simple project in quartus ii v7.2, it containe a schematic file with three gates. I compiled it but haven't generated the .sof file. So, when i go to load my project to the board there isn't .sof file

Could help me anyone?
Thanks!
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Could find (down load MAX+PLUS ii baseline version 10.0

December 29, 2014, 12:32 pm
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Hi, I woring with maintenance of old industrial equipment and many time need to upgrade FPGA (7000S serie).
To migret to windows 2000 or XP I need to start with max+plus 10.0 that still alloes using byte blaster MV for in circuit upgrading. Could one tell me vhere on Altere download/support place could I find that version?
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Results of Verilog debugging problems

December 28, 2014, 7:40 pm
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The design of a level sensitive latches, input signal is d clock, the output for the Q, the function is clock=1, q=d

My code is as follows, the problem is the simulation results in clock=1, q=d no problem, but clock=0 should be maintained in front of Q value, and the result is q=d; please have a look of code where the problem

module my_latch(d,clock,q);
input clock;
input [3:0] d;
output [3:0] q;
reg [3:0] q;
always
wait (clock)
begin
#1 q<=d;

end
endmodule

module stimulus_latch;
reg CLOCK;
wire [3:0] Q;
reg [3:0] D;

my_latch MY_LATCH(D,CLOCK,Q);
initial
begin
CLOCK <= 1'b0;
forever #20 CLOCK=!CLOCK;
end
initial
begin
#20 D=4'D7;
#20 D=4'D12;
#20 D=4'D5;
#20 D=4'D13;
#200 $stop;
end
initial
$monitor($time ," D= %B,Q= %B ",D[3:0],Q[3:0]);
Endmodule
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can i read 2 input analog in DE0 nano without switch selector???

December 28, 2014, 8:51 pm
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i read the manual book that explain DE0 nano have IC ADC to read analog data but it's just can access 1 pin in one time using a switch selector, then i read the program demo on deo nano sample itls using pin from switch selector can i read without switch selector (in program below)???. i try to change with biner value but nothing effect it's just read input with pin selector switch that selected, did someone experience read the analog in DE0 Nano like this can you help me ???



Program ADC_control demo

module ADC_CTRL (
iRST,
iCLK,
iCLK_n,
iGO,
iCH,
oLED,

oDIN,
oCS_n,
oSCLK,
iDOUT
);

input iRST;
input iCLK;
input iCLK_n;
input iGO;
input [2:0] iCH;
output [7:0] oLED;

output oDIN;
output oCS_n;
output oSCLK;
input iDOUT;

reg data;
reg go_en;
wire [2:0] ch_sel;
reg sclk;
reg [3:0] cont;
reg [3:0] m_cont;
reg [11:0] adc_data;
reg [11:0] nilaiadc;
reg [7:0] led;

assign oCS_n = ~go_en;
assign oSCLK = (go_en)? iCLK:1;
assign oDIN = data;
assign ch_sel = iCH;
assign oLED = led;

always@(posedge iGO or negedge iRST)
begin
if(!iRST)
go_en <= 0;
else
begin
if(iGO)
go_en <= 1;
end
end

always@(posedge iCLK or negedge go_en)
begin
if(!go_en)
cont <= 0;
else
begin
if(iCLK)
cont <= cont + 1;
end
end

always@(posedge iCLK_n)
begin
if(iCLK_n)
m_cont <= cont;
end

always@(posedge iCLK_n or negedge go_en)
begin
if(!go_en)
data <= 0;
else
begin
if(iCLK_n)
begin
if (cont == 2)

data <= iCH[2]; //selektor switch

else if (cont == 3)

data <= iCH[1]; //selektor switch

else if (cont == 4)

data <= iCH[0];//selektor switch

else
data <= 0;
end
end
end

always@(posedge iCLK or negedge go_en)
begin
if(!go_en)
begin
adc_data <= 0;
led <= 8'h00;
end
else
begin
if(iCLK)
begin
if (m_cont == 4)
adc_data[11] <= iDOUT;
else if (m_cont == 5)
adc_data[10] <= iDOUT;
else if (m_cont == 6)
adc_data[9] <= iDOUT;
else if (m_cont == 7)
adc_data[8] <= iDOUT;
else if (m_cont == 8)
adc_data[7] <= iDOUT;
else if (m_cont == 9)
adc_data[6] <= iDOUT;
else if (m_cont == 10)
adc_data[5] <= iDOUT;
else if (m_cont == 11)
adc_data[4] <= iDOUT;
else if (m_cont == 12)
adc_data[3] <= iDOUT;
else if (m_cont == 13)
adc_data[2] <= iDOUT;
else if (m_cont == 14)
adc_data[1] <= iDOUT;
else if (m_cont == 15)
adc_data[0] <= iDOUT;
else if (m_cont == 1)
nilaiadc <= adc_data[11:4];
end

end

endmodule
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How to implement a 32K lookup table in CPLD?

December 29, 2014, 12:53 pm
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hello,
I'm newbie in VHDL, FPGAs and CPLDs devices. I would like some help for implement a lookup table with 2048 words (2 bytes).
The table should be: 2048x16bits (32K), I mean, 11 bits address (A10-A0) and 16 bits data (D15-D0). As soon as the address is placed on the bus, the fastest possible data should appear (no latch or enable is used).

Please, could somebody guide in the implementation? Can I use a CPLD (EPM240 o EPM570)?
I need to use the fewest possible components, so I prefer a CPLD.

This the code I plan to use, but I think it will be very slow due to sequential process (assume that the latest addresses are used):
-----------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY lookuptable IS
PORT (address : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
data : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
) ;
END lookuptable ;

ARCHITECTURE behavior OF lookuptable IS
BEGIN
PROCESS ( address )
BEGIN
CASE address IS
WHEN "00000000000" => data <= "1111111111111111"; -- example data, all "1s"
WHEN "00000000001" => data <= "1111111111111111"; -- example data, all "1s"
WHEN "00000000010" => data <= "1111111111111111"; -- example data, all "1s"
WHEN "00000000011" => data <= "1111111111111111"; -- example data, all "1s"
.
.
.
WHEN "11111111101" => data <= "1111111111111111"; -- example data, all "1s"
WHEN "11111111110" => data <= "1111111111111111"; -- example data, all "1s"
WHEN "11111111111" => data <= "1111111111111111"; -- example data, all "1s"
WHEN OTHERS => data <= "0000000000000000"; -- example data, all "0s"
END CASE;
END PROCESS;
END behavior
-----------------------------------------------------------------------

I know that altsyncram (with ROM, single-port) Megafunction option exist , but this will force to use a FPGA device (more expensive and need more electronics components around it). That is my last option.

Thank you !
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[Question about synchronous transfer] Will this kind of transfer cause problem?

December 29, 2014, 7:26 pm
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I know for any asynchronous data transfers, we would need special handling mechanisms (i.e double sync, FIFO, handshaking, etc). I have a design that where the core logic interacts with the LVDS TX IP block using 2 PLLs. The launch clock (that feed the core reg) is from the 1st PLL. The latch clock (that feeds the tx_reg from LVDS) is from 2nd PLL, but is also sourced from the first PLL. These 2 clocks have the same frequency but different phase. In this case, is this kind of transfer still considered synchronous or will it run into metastability issue despite meeting timing requirement in TQ?

I attached a diagram for better illustration. The transfers that I posted is from Core Reg --> tx_reg


​Thank you.
Attached Images
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Endianess of Avalon-ST Packets to PCI Express TLPs for IP Compiler for PCI Express

December 29, 2014, 10:48 pm
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Hi, we are using PCIE Express Hard IP to interface both PowerPC and Intel X86.

The difference that influences our FPGA user logic is the endianness of two processors.

PowerPC is Big endian while Intel X86 is little endian.

From IP Compiler for PCI Express User Guide, Mapping of Avalon-ST Packets to PCI Express TLPs is below:

Notes to Figure 5–17:
(1) Header0 ={pcie_hdr_byte0, pcie_hdr _byte1, pcie_hdr _byte2, pcie_hdr _byte3}
(2) Header1 = {pcie_hdr_byte4, pcie_hdr _byte5, header pcie_hdr byte6, pcie_hdr _byte7}
(3) Header2 = {pcie_hdr _byte8, pcie_hdr _byte9, pcie_hdr _byte10, pcie_hdr _byte11}
(4) Data0 = {pcie_data_byte3, pcie_data_byte2, pcie_data_byte1, pcie_data_byte0}
(5) Data1 = {pcie_data_byte7, pcie_data_byte6, pcie_data_byte5, pcie_data_byte4}
(6) Data2 = {pcie_data_byte11, pcie_data_byte10, pcie_data_byte9, pcie_data_byte8}.

It seems headers are little endian, payloads are big endian.

Is there any configuration about endianness needed to be set?

How does this IP process the endian difference?
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Endianess of Avalon-ST Packets to PCI Express TLPs for IP Compiler for PCI Express

December 29, 2014, 10:51 pm
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Hi, we are using PCIE Express Hard IP to interface both PowerPC and Intel X86.


The difference that influences our FPGA user logic is the endianness of two processors.


PowerPC is Big endian while Intel X86 is little endian.


From IP Compiler for PCI Express User Guide, Mapping of Avalon-ST Packets to PCI Express TLPs is below:


Notes to Figure 5–17:
(1) Header0 ={pcie_hdr_byte0, pcie_hdr _byte1, pcie_hdr _byte2, pcie_hdr _byte3}
(2) Header1 = {pcie_hdr_byte4, pcie_hdr _byte5, header pcie_hdr byte6, pcie_hdr _byte7}
(3) Header2 = {pcie_hdr _byte8, pcie_hdr _byte9, pcie_hdr _byte10, pcie_hdr _byte11}
(4) Data0 = {pcie_data_byte3, pcie_data_byte2, pcie_data_byte1, pcie_data_byte0}
(5) Data1 = {pcie_data_byte7, pcie_data_byte6, pcie_data_byte5, pcie_data_byte4}
(6) Data2 = {pcie_data_byte11, pcie_data_byte10, pcie_data_byte9, pcie_data_byte8}.


It seems headers are little endian, payloads are big endian.


Is there any configuration in Megawizard about endianness to set?


How does this IP process the endian difference?
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STA and Timequest relation

December 29, 2014, 11:55 pm
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Hello everyone, i am fresher to VLSI fiels. I am doing Verilog/VHDL coding for last 10 months. I come across these back end terms of Constraining, Timing and fitting the design on FPGA. I read about them on internet like what constrains do, STA is important and can be done on different level and other information. I have few questions based on that Hope u reply and put me out of my curiosity.

1. What does TimeQuest do?
2. Difference between constraining the design and performing STA?
3. I am fresher, so how to know what values to put in constrain column?
4. How STA is performed?

Help me out, i will study and work hard JUST GUIDE ME.
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Cyclone iii developpment board: DVI problem

December 30, 2014, 2:33 am
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Hello all,

I create a Sopc system to test my dvi output but it does'nt work. I use a test pattern and a clocked video output, it's a simple system. I use a clock of 108Mhz for a resolution of 1920*1080. what can I do to have a picture in my screen?

Cordially
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vip_top for video example design

December 30, 2014, 2:44 am
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Hello all,

I want to to use the eample design video donné par altera but I can't find the .bdf file that contains the graphic modules. I f someone have this example please I need it.

Cordially
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PLL Locking - Transient input clock

December 30, 2014, 6:05 am
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Hello,

I am hoping someone can offer a bit of advice with respect to using a PLL to lock to a clock that is transient. Currently I have the differential clock signal entering on an clock input pin in an Arria V device. My problem is that the clock is switched off by the source between data packets. There is a small window of about 150ns in which the clock is running, prior to data begining. I was hoping to use Altera PLL to lock to this clock when its available, in order to take advantage of the verious skew related options that are offered, so that the clock is phase adjusted at the PLL output to be syncronous with the pin's input.

However, after playing around with the PLL, the lock time is just too slow, so that by the time the PLL has locked the data has already begun to transmit. The obvious solution is to use the input clock directly, and adjust the data lines for any skew on the clock line. This is the approach I am currently taking, but I would love to know if there is any technique to enable quicker locking on the PLL.

Additionally, as the input data is serial, I would like to also try using the transceivers to receive the data, but I am still a bit confused on whether or not I can do this with a clock that is transient. It seems that I could provide my own internal clock to the transciever and use the CDR stuff to recover the clock from the input data alone? and ignore the clock that is transmitted with the data?

Any advice or comments is greatly appreciated.

rma.
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Quartus 2 13.0sp1 Hardware debugging issue

December 30, 2014, 7:02 am
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Hello,

I have started using the DE0 board, normally i write my code in C then debug it as hardware on the DE0 for certain Universitie projects, the issue that I'm facing is that on one of my PCs the debugger runs but it does not upload the programme to the board or retrieve the value of variables once the debugger is paused, when the debugger is paused this [No source available for ""] appears , I don't seem to have this issue with my other PC , no error message appears on the screen either, i have tried re-installing the software several times, i have also re-installed windows and made sure all drivers are up to date.

the driver for the DE0 board is installed manually from the programmes directory as on my other PC which doesn't give an issue, I'm really struggling to solve the issue and it seems like no one has faced it before, would any one make a suggestion of what i can do, i would be realy greatful.

many thanks
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