January 18, 2015, 4:32 am
Hello,
I am trying to implement direct DMA communication between a Nvidia Quadro and a Stratix V board over PCIe. Nvidia supports this with its GPUDirect RDMA technology. I have read through the code of Altera's PCIe driver and as far as I can tell I only need to get the physical address of the GPU memory and send it to the DMA controller, is that correct?
I already succeeded to transfer data from the FPGA to the GPU that way, however when I try the other direction (by swapping read and write addresses), the whole system freezes.
My kernel module code looks something like this (simplified & error checking omitted):
Code:
//pin gpu memory and get the physical address
nvidia_p2p_get_pages(0, 0, virtual_gpu_address, size, &page_table, free_callback, NULL);
unsigned long physical_gpu_address=page_table->pages[0]->physical_address;
//set up a dma descriptor
unsigned int att_row=0;
size_t pcietxs_addr = (size_t) ACL_PCIE_TX_PORT
| (att_row * ACL_PCIE_DMA_MAX_ATT_PAGE_SIZE)
| (physical_gpu_address & (ACL_PCIE_DMA_MAX_ATT_PAGE_SIZE-1));
struct DMA_DESCRIPTOR dmadesc;
//direction from FPGA to GPU (works)
//dmadesc.read_address= LO32(fpga_address);
//dmadesc.read_address_hi= HI32(fpga_address);
//dmadesc.write_address= LO32(pcietxs_addr);
//dmadesc.write_address_hi=HI32(pcietxs_addr);
//direction from GPU to FPGA (crashes)
dmadesc.read_address= LO32(pcietxs_addr);
dmadesc.read_address_hi= HI32(pcietxs_addr);
dmadesc.write_address= LO32(fpga_address);
dmadesc.write_address_hi=HI32(fpga_address);
dmadesc.bytes = size;
dmadesc.burst = 0;
dmadesc.stride = 0x00010001;
dmadesc.control = (unsigned int)( ACL_PCIE_GET_BIT(DMA_DC_GO)
| ACL_PCIE_GET_BIT(DMA_DC_EARLY_DONE_ENABLE)
| ACL_PCIE_GET_BIT(DMA_DC_TRANSFER_COMPLETE_IRQ_MASK)
);
//send data to the DMA controller
//functions from aclpci_dma.c
set_att_entry(aclpci, physical_gpu_address, att_row);
dma_desc_write (aclpci, 0, &dmadesc);
Does anyone have an idea what could be wrong?
Thanks,
Alexander
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January 18, 2015, 12:40 pm
Hello,
This is my first post. I'm trying to get acquainted with Quartus 2 and my Altera FPGA board but I'm having problems starting.
Firstly when I'm in Quartus I can't seem to find my device. I'm using a cyclone 3 EP3C16F484C6N and I do not see "cyclone 3" listed in the "family" pull down menu under the family & device settings nor do I see the EP3C16F484C6N listed in available devices.
Secondly, I don't know whether this is a big issue or not, but I can't seem to get my DE0_controlPanel to work. I think I successfully installed the drivers for the board. However when I try to open the DE0_controlPanel I get errors like:
"The program can't start because jtag_client.dll is missing from your computer. Try reinstalling the program to fix this problem"
"Load DLL (TERASIC_JTAG_DRIVE.dll) fail"
"Please make sure Quartus is installed" (it is and I can run it)
"download SOPC file (DE0_ControlPanel.sof) fail!"
I don't know whether this is a good idea but when I move the jtag_client.dll file from Quartus to the file in which the DE0_controlPanel is in then I can make the first error go away. Someone suggested I should also move the dinkum_alt.dll file in there as well but I can't find it.
Any help would be appreciated. Thank you.
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January 18, 2015, 2:03 pm
Hello,
I'm building Linux kernel and root filesystem for Arrow SoCKit.
I've installed cross compiler on Ubuntu 14.10 machine:
$ sudo apt-get install gcc-arm-linux-gnueabihf
$ arm-linux-gnueabihf-gcc --version
arm-linux-gnueabihf-gcc (Ubuntu/Linaro 4.9.1-16ubuntu6) 4.9.1
Copyright (C) 2014 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
The cross-compiler works. I've used it to build kernel for Arrow SoCKit:
$ make CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm socfpga_defconfig
$ alias armmake='make CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm' <--I put this into .profile
$ armmake -j4 uImage LOADADDR=0x8000 <-- this produced the expected uImage
But then I run into problem trying to build root fs for SoCKit using Buildroot-2014.11:
$ make menuconfig
Within Buildroot menuconfig I set the Toolchain as follows:
Toolchain type (External toolchain) --->
Toolchain (Custom toolchain) --->
Toolchain origin (Pre-installed toolchain) --->
(/usr/) Toolchain path
(arm-linux-gnueabihf) Toolchain prefix
External toolchain kernel headers series (3.1.x) --->
External toolchain C library (glibc/eglibc) ---> [*] Toolchain has RPC support? [*] Toolchain has C++ support?
() Extra toolchain libraries to be copied to target
[ ] Copy gdb server to the Target
[ ] Build cross gdb for the host
[ ] Purge unwanted locales
() Generate locale data
[ ] Copy gconv libraries [*] Enable MMU support
(-pipe) Target Optimizations
() Target linker options
[ ] Register toolchain within Eclipse Buildroot plug-in
Then run make and get the following error:
$ make
/usr/bin/make -j1 HOSTCC="/usr/bin/gcc" HOSTCXX="/usr/bin/g++" silentoldconfig
make[1]: Entering directory '/home/jeff/buildroot-2014.11'
BR2_DEFCONFIG='' KCONFIG_AUTOCONFIG=/home/jeff/buildroot-2014.11/output/build/buildroot-config/auto.conf KCONFIG_AUTOHEADER=/home/jeff/buildroot-2014.11/output/build/buildroot-config/autoconf.h KCONFIG_TRISTATE=/home/jeff/buildroot-2014.11/output/build/buildroot-config/tristate.config BR2_CONFIG=/home/jeff/buildroot-2014.11/.config BR2_EXTERNAL=support/dummy-external /home/jeff/buildroot-2014.11/output/build/buildroot-config/conf --silentoldconfig Config.in
make[1]: Leaving directory '/home/jeff/buildroot-2014.11'
>>> toolchain-external undefined Configuring
cc1: fatal error: /usr/arm-linux-gnueabihf//usr/include/linux/version.h: No such file or directory
compilation terminated.
support/scripts/check-kernel-headers.sh: 38: support/scripts/check-kernel-headers.sh: /tmp/check-headers.uAeguv: Permission denied
package/pkg-generic.mk:172: recipe for target '/home/jeff/buildroot-2014.11/output/build/toolchain-external-undefined/.stamp_configured' failed
make: *** [/home/jeff/buildroot-2014.11/output/build/toolchain-external-undefined/.stamp_configured] Error 1
I've used Buildroot in Arch Linux without encountering the above problem. I'm new to Ubuntu, and can't figure out what is going wrong.
Can anyone help? Thanks!
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January 18, 2015, 5:32 pm
Been trying to install Quartus II on my personal Dell Inspiron dual core laptop ,running Windows 7, for three days. Tried everything including disabling firewall. Akamai keeps asking to choose new folder, over and over again. I can download files manually but get error when i try running executable. Nothing works.
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January 18, 2015, 9:05 pm
I'm considering SRunner tools to edit my .rpd files. However I didn't find any files about this tool. Is there any handbooks of this tool? Or do I need to read the source code of this tool?
BTW, is there any tools that have similar function of editiing the .rpd files?
Any suggestions can be helpful!
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January 19, 2015, 3:30 am
![]()
The eclipse-nios2 won't start in Quartus ii version 13.0sp1 installed in Ubuntu 14.04.
as in the picture when i start the nios2-command_shell from the terminal and then try to open eclipse-nios2 it won't start and nothing shows up. any suggestion?
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January 19, 2015, 10:21 am
Hello all,
I have a simple custom Avalon MM-Master component
Code:
-- Avalon Master Sample Memory Writer
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity avalon_mem_writer is
port
(
avm_clk : in std_logic;
avm_reset : in std_logic;
avm_address : out std_logic_vector(31 downto 0);
avm_write : out std_logic;
avm_writedata : out std_logic_vector(7 downto 0);
avm_waitrequest : in std_logic
);
end entity;
architecture rtl of avalon_mem_writer is
type state_type is (idle_state, write_state);
signal state : state_type;
signal avm_address_index : unsigned(31 downto 0);
begin
process (avm_clk, avm_reset)
begin
if avm_reset = '1' then
state <= idle_state;
avm_address_index <= x"00000000";
elsif (rising_edge(avm_clk)) then
case state is
when idle_state =>
if(avm_waitrequest='0') then
state <= write_state;
end if;
when write_state =>
avm_address_index <= avm_address_index + 1;
if(avm_address_index = x"0000000FF") then
avm_address_index <= x"00000000";
end if;
if(avm_waitrequest='1') then
state <= idle_state;
end if;
end case;
end if;
end process;
avm_address <= x"00000000"; -- std_logic_vector(avm_address_index);
avm_writedata <= std_logic_vector(avm_address_index(7 downto 0));
process (state)
begin
case state is
when idle_state =>
avm_write <= '0';
when write_state =>
avm_write <= '1';
when others => null;
end case;
end process;
end rtl;
that simply write continuosly to onchip-memory.
I want to share On-chip memory used by my component with NIOS CPU but if I connect both onchip memory isn't written.
Should I connect another component (maybe an arbiter) between memory and masters or is automatically inserted?
Thnak you
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January 19, 2015, 10:23 am
There is some simple example for doing DMA between an Avalon streaming source and a memory shared with CPU?
I have seen SGDMA but C API seem very complex..
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January 19, 2015, 10:29 am
Hi,
I have been trying to use the board test system for the Stratix V DSP development kit, but when I try to load it, I get a message saying the active version of Quartus is 9.0 but it needs to be 12.0. I did have v9 installed, but I have since removed that. Currently I have 13.1 and 14.0 installed.
So how on earth do I set the 'Active Version'? I have found reference to this sort of issue with the Stratix IV board test system, but nothing anywhere which actually says how to set the 'active version'.
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January 19, 2015, 12:04 pm
Hello,
I am using a Fifoed UART for reading characters from the serial interface.
I found that getchar() is blocking when no characters are present in the fifo which I cannot use.
Is there a way to determine if there are characters present in the read fifo.
I can use this signal then for reading them then with getchar().
Thank you all for your responses.
Regards,
Wamor
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January 20, 2015, 2:24 am
Hello friends,
I am using Altera Cyclone III FPGA Starter board (EP3C25F324) for controller design for my DC-DC power converter.
When I start 'Board Test System' or run control panel app that comes with the altera cyclone III starter kit, the following error message appears :
![]()
'Could not establish JTAG connection between the board and control panel application.'
I have installed Cyclone III starter kit 12.0.0, Quartus II web edition version 12.0 and USB blaster version 2.4.16.0 on my computer which is having windows 7, 32-bit operating system.
Please help me to solve this problem as it is hampering my work.
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January 20, 2015, 4:08 am
hi
i am using 5csxfc6c6u23i7n device (cyclone5 soc).
i want to use its gpio pins, and i need a proper schematic of it
regards!
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January 20, 2015, 4:08 am
That I may access the inputs and outputs of my code during emulation, I have to modify the code for that or during emulation is done automatically?
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January 20, 2015, 4:48 am
I have several ModelSim_AE floating licenses. With these licenses, VSIM stars but then failed on ELAB with the following error message:
# Top level modules:
# test
# End time: 09:56:12 on Jan 20,2015, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# work.test
# [exec] elab
# vsim
# Start time: 09:56:12 on Jan 20,2015
# ** Error: Failure to obtain a Verilog simulation license. Unable to checkout any of these license features: alteramtivsim or alteramtivlog.
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./scripts/test_ready_1_always.tcl PAUSED at line 29
The error message is similar to this one
http://www.altera.com/support/kdb/so...202011_86.html
I run ModelSim on Ubuntu14.04. Does it imply that I need a "Windows Terminal Server remote feature"?
Is it possible to use ModelSim_AE under Linux with a floating license?
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January 20, 2015, 5:54 am
My design is such that I will require all transceiver channels to be full duplex(both transmit and receive). I have instantiated a PCIexpress module with uses one of the channels as a global PLL for the bonded x4 pciexpress transmitter PLL. I however do not want to use this channel as transmitter PLL(it will be used for another high speed link later) I have read in a lot of Altera literature that it is possible to use the normal fpll for clocking the transmitter up to a speed of about 3Ghz). This will meet my requirement but the big question is how do I connect the fpll output to the transceiver?
Using Arria V SoC
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January 20, 2015, 6:22 am
Hi
I would like to post here my problem with ModelSim Altera starter edition 10.1e. I have been using it for last few month without a problem. But suddenly it doesnt do anything when i r-click on some .vhd file and select "compilate selected" or "compilate all". No error, no waiting cursor, simply no visible or any other reaction. Same problem when i want to run compilation through menu on the top of modelsim window. Same problem on school PC, same problem when new project started. First time it happened was in school. I have opened and saved files manytimes in school and on my PC alternately. Have someone an experience like me? My project is situated on flash drive, but every file is OK, i think, because it can be written, saved and simulated without problem. Only think that doesnt work is compilation. Thank you very much.
Jan Siroky
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January 20, 2015, 7:29 am
Hello All,
The exportation of the logic devices is controlled in the EU.
If the device has "an aggregate one-way peak serial transceiver data rate of 200 Gb/s or greater", the device is Dual Use part so the exportation is regulated by the EU law.
Aggregate one-way peak serial transceiver data rate is the product of the peak serial one-way transceiver data rate times the number of transceivers on the FPGA.
I would like to get help to determine wich devices exceed the 200Gb/s limit.
I found the following information so far:
link:
http://www.altera.com/technology/high_speed/hs-index.html
Here I can found which products contains serial transceivers.
According to the datasheets we can calculate the the data rate multiplying the transceiver count by the transceiver speed.
But it would be very helpful, If someone with the neccessary technical knowledge could help me, wich exact part numbers has greater than 200 Gb/s serial transceiver data rate.
I mean a list of part numbers which exceed the above limit.
Many Thanks,
Bela Farkas
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January 20, 2015, 11:07 am
One of my task is to make PI controller for DC drive. I decided to make it's in vhdl. I prepare following code:
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pid is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
data_en : in STD_LOGIC;
set_point : in STD_LOGIC_VECTOR (15 downto 0);
fb : in STD_LOGIC_VECTOR (15 downto 0);
pi_o : out STD_LOGIC_VECTOR (31 downto 0));
end pid;
architecture Behavioral of pi is
begin
process(clock) is
variable p,i,result: signed(pi_o'range);
begin
if rising_edge(clock) then
if reset = '1' then
i := (others => '0');
elsif data_en = '1' then
p := signed((set_point - fb)* "0000000000000011"); -- data-fb is the error
i := i + signed((set_point-fb) * "0000000000000010");
result := (p + i);
end if;
pi_o <= std_logic_vector(result);
end if;
end process;
end Behavioral;
I have question if it's correct? All variables are initialized correctly? I ask this stupid questions because we don't have enough access to Altera fpga boards.
Code:
i := i + signed((set_point-fb) * "0000000000000010");
In this line I think that I should add something more, it should be divide by something, but I don't know by what?
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January 20, 2015, 12:05 pm
I am wondering if there is a way to specify the LUT_inputs and lock them for a given LUT. The reason I am doing this: I am creating delay lines using chains of inverter gates. If I allow the optimizer to create the delay lines, then some of the LEs have inputs on port C while others are on port D. This is problematic because, without control, the delay is varied (port C has a longer delay than port D). Thus, I would like to have arbitrary control over each LE with regards to the LUT and the specific LUT input pins used. What do you think?
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January 20, 2015, 12:37 pm
Im trying to create an array of vectors like shown in the code below:
type ram256 is array (0 to 255) of std_logic_vector (11 downto 0);
signal memoria: ram256;
The problem is that, initially i only use about the first 25 vectors of the type. I need the other ones to be 0 but since they're 256 vectors in total, its too long to do it manually. Can anyone help me how to do it? I tried with for loop but when i use the test bench after, it seems like the memory its full of U's.
Thank you very much in advance.
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