In out project we have implemented a Custom PHY transceiver, running in duplex mode at 5120 MHz, and the loop-back is done externally with a fibre. Through the TX link we send 191 bits (6 lanes with 32 bits each) with the next pattern:
The pseudo-random pattern is a 128b word, with a 4b header (0101), and starts with a counter so it is easily spotted in SignalTap (see attached screen-shots).
In the RX side, we receive the next:
By "wrong" I mean that the header it is now "1111" instead of "0101" and the counter instead of been 0-1-2-3-4-5-6 is 0-3-6-7-12-15-14. In addition, the counter's bits have been moved 1 clock cycle ahead. Where in the tx lanes the counter bits are 3 clock cycles after the header, in the rx side they are in the 2nd clock cycle. In the attached files it is more clear what I wanted to say.
More information about our setup:
We already try:
Any suggestions?
And thanks in advance.
- FFFF0000FFFF0000 from 191 downto 128
- AAAAAAAAAAAAA from 127 downto 64
- know pseudo-random pattern from 63 downto 0
The pseudo-random pattern is a 128b word, with a 4b header (0101), and starts with a counter so it is easily spotted in SignalTap (see attached screen-shots).
In the RX side, we receive the next:
- FFFF0000FFFF0000 from 191 downto 128
- AAAAAAAAAAAAA from 127 downto 64
- wrong pseudo-random pattern from 63 downto 0
By "wrong" I mean that the header it is now "1111" instead of "0101" and the counter instead of been 0-1-2-3-4-5-6 is 0-3-6-7-12-15-14. In addition, the counter's bits have been moved 1 clock cycle ahead. Where in the tx lanes the counter bits are 3 clock cycles after the header, in the rx side they are in the 2nd clock cycle. In the attached files it is more clear what I wanted to say.
More information about our setup:
- Quartus 13.1
- Stratix V 5SGXEA7N2F45C3
- FPGA fabric transceiver interface width = 32
- Number of lanes = 6
- "Data rate" and "base data rate" = 5120 Mbps
- Input clock frequency = 160 MHz
- rx_signaldetected and rx_is_lockedtodata are asserted in all the lanes
- The pseudo-random words are 128b wide, but are sent in packets of 32b, that's why after the header there are two clock cycles without data, and in the 3rd in where the counter bits are.
We already try:
- Enable rx_coreclkin and tx_coreclkin and link them to a 160 MHz clk without any change in the behaviour.
- Internal loop-back, but that option seems not to be present in the Megafunction window. Nevertheless we manually edited the .sv files to change the "ser_loopback" parameter to "true", but it did not worked.
Any suggestions?
And thanks in advance.