[U-boot] bridge_enable_handoff failed to run

December 7, 2015, 3:13 am

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Hi All,

When I run the bridge_enable_handoff command (run bridge_enable_handoff), I receive the following:
## Starting application at 0x3FF79720 ...
## Application terminated, rc = 0x0


The FPGA is programmed and works.


What's wrong?

Thank you!

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[U-boot] i2c probe -> no valid chip addresses

December 7, 2015, 4:26 am

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Hi All,

When I run the i2c probe u-boot command, I'm receiving the following:

Code:

---

i2c probeValid chip addresses:
SOCFPGA_ARRIA5 #

---

What does it mean? Was no i2c devices detected on the i2c bus?

Thank you!

OpenCL SDK support for Arria 10 SoC Development Kit

December 7, 2015, 4:58 am

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Hi,

Does anyone know if the new Arria 10 SoC Development Kit supports (or will support) the SDK for OpenCL, as the Cyclone V SoC Development Kit did?

Sincerely,

Hugh

NetList Viewer RTL from the command line

December 7, 2015, 6:15 am

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hi,
I wonder what is the approprioate command to display my project Netlist Viewer RTL using the prompt line?
I tried this one, however it does not show any RTL, assuming that I already compiled the project.
quartus_rpp assignment2 -c counter --netlist_type=sgate

It is possible to run altera_avalon_uart at 921600 bps?

December 7, 2015, 7:56 am

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It is possible to run altera_avalon_uart at 921600 bps instead of 115200?
QSys GUI have only 115200 but with some code there is possibility?

Thanks

Implementation of Bluetooth in FPGA (DE2-115)

December 7, 2015, 8:30 am

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Hi everyone! I'm a newbie in using FPGA. Currently I'm using Terasic VEEK-MT which features DE2-115 development board. And I'm using the VEEK-MT hardware demo code and build my software on top of that.

I would like to receive data sending from Arduino(using BlueBee). However, I have no idea on how to receive the data in FPGA using bluetooth.
I would like to ask what will be a good choice to implement this?
I have been thinking of using a Bluetooth to RS-232 port adapter to receive the data.
Is it possible? and how can I achieve this?
Thanks a lot for your help!!

Vhdl jpeg decoder

December 7, 2015, 8:47 am

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Hi, I am working on a project where I need to implement a JPEG decoder to decode the JPEG output (1080p) of the camera (model: OV5642). My FPGA is DE1-SoC Cyclone V. I have been able to implement a jpeg decoder in the ARM processor using C, which works fine; but its speed does not satisfy my project's requirements. So, the solution that comes to my mind is to move the jpeg decoder to the FPGA side. However, I have not been able to find a jpeg decoder that merely works on the FPGA, not the processor. Actually, I have found one at opencores, however, the code uses ip cores from xilinx. My question is: do you know a jpeg decoder implemented in VHDL that I could use on an Altera FPGA? It would be very nice if you could state whether it is free or not. Thank you.

The Configured Quartus II version [10.1sp1] Mismatch with NIOS II [9.0]

December 7, 2015, 10:33 am

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How do I get around this issue???

"Nios II EDS Version Check"
"The configured Quartus II [10.1sp1] does not match the current NIOS II EDS version [9.0]."

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PCIE DMA stratixV simulation with modelsim 10.4c

December 7, 2015, 1:10 pm

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Hi,

I would like to simulate the v-series AVMM PCIE DMA example design under altera/14.0/ip/altera/altera_pcie/altera_pcie_hip_256_avmm/example_design/sv/
I am using quartus II 14.0 and ModelSim SE-64 10.4c.

The test benches are generated in Qsys. Every time I tried to execute the "ld_debug", Modelsim will quit. There is no problem to compile necessary Altera libraries with the vlog commands. But it seems the elaboration caused the problem. The message shown on terminal is "Bad pointer access... Closing wish.' after the vsim dropped.

Any idea why this might happen?

Thanks.

NIOS f core Barrel Shifter & dynamic branch prediction

December 7, 2015, 5:48 pm

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Hi,

I want to know if the Barrel Shifter and the Dynamic Branch Prediction Options in the NIOS II (f)ast core is configurable

Thanks a lot in advance

Timing Error with RGMII CycloneV SoC

December 7, 2015, 6:03 pm

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Hi. I'm "720_com" of Altera beginner.
I want to solve the timing violation message.


Design : Cyclone V RGMII Example Design
http://rocketboards.org/foswiki/view...IExampleDesign


I found same topics. But, there is no writing it.
http://www.alteraforum.com/forum/showthread.php?t=50845
So, I'm in trouble.



<Timing violation path>
Setup Timing violation path : TX_CLK_OUT_125


I am trying the below( 9 paths);
http://www.alteraforum.com/forum/showthread.php?t=46960


It is look like timing violation.


I want solve timing error. Please tell me about solve it.


If anyone has any idea, please tell me.
Thanks in advance.

Attached Images

• timing_violation.JPG (529.2 KB)

Attached Files

• cv_soc_rgmii_5csxfc6_ver15.0.qar (1.92 MB)

vsim 3033 error of "The design Unit not found" of modelsim

December 7, 2015, 9:58 pm

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hi..
there is some problem in simulating the design. I have added a FIR Filter in the design but it is not simulating and the error message of vsim 3033 is displayed in the prompt.
may be some library need to be added.
any help will be appreciated.

Java returned exit code / Nios II

December 8, 2015, 7:33 am

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Hi all!
I am a new user in this forum, I have looked for information about my problem but I did not find too much information.
I have the next issue:
When I want to run/debug my C code using Nios II a trouble with Java SE appears. The problem is showed when I was using my DE0 board an Nios II 12.0.
I have attached a window showing my problem, I hope you can help me.
Thanks in advance.

Attached Images

• error.jpg (19.9 KB)

Question about good design: overriding functions, function parameters or similar

December 8, 2015, 7:40 am

≫ Next: Altera CDF MfrSpec field

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Hi,
Is in VHDL something similar to overriding a function or giving function as parameter to an entity (similar to c++ or javascript).

I'm implementing some image processing components which are similar to each other up to one or two functions which I use to calculate pixel values. I want to create one entitiy and provide different functions as parameters to this entity. I can't export signals and compute values outside of entity because function is used inside in several places, in for loops etc.
What is the best way to implement this?

My current idea is to create a large main function which calls other small functions according to parameter given to entity. The entity always calls the main function and gives a selection parameter.

Altera CDF MfrSpec field

December 8, 2015, 8:06 am

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Hello,

Is there any way of getting information about the contents of the MfrSpec in the .cdf programming files?

For instance, what does (OpMask(0) Child_OpMask(2 1 0)) or (OpMask(1) Child_OpMask(2 1 128)) mean for a MAX10 FPGA?

Thank you in advance.

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40bits floating points audio (cyclone V)

December 8, 2015, 9:48 am

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Hi
I was wondering if 40 bits floating point math operations (for audio processing and filtering such ad IIR filters,...) can be supported by DSP builder in cyclone-V devices?
Thanks,
Farhad

SPI Core without AXI/Avalon interface

December 8, 2015, 1:16 pm

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Hi All,

I need a SPI Core, which is able to receive a hardware trigger in order to start its transmission.

It should not be connected neither to Avalon nor AXI3 buses. All the configurations (clock polarity, etc) should be done/configured during the core creation.

Does Altera has such core? The only SPI Core, which I found in the IP-Catalog, is the Avalon-ST Serial Peripheral Interface (SPI). This Core does require the Avalon/AXI3 connection.

So, do you have a Core, which might be instantiated in the FPGA portion of ArriaV and which does not require a connection to HPS?

Thank you!

Linux and Programming the FPGA

December 8, 2015, 3:56 pm

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Hi
When we boot DE1-SOC with a Linux, it is possible to put a rbf file in the root directory and during the boot process that file will be used to program the FPGA. I was wondering if there is any solution to program the FPGA directly with Quartus when we boot the board with Linux.


Best,

Cannot enumerate/read USB mass storage if Linux booted from USB

December 8, 2015, 5:45 pm

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Hello,

I am trying to boot from the USB2.0 OTG port on my Altera SoCKit board (from Terasic), running Linux 3.18.20. I have a strange problem that I have tried to isolate as much as possible.

Given: I have a Linux zImage and a dtb file. The zImage includes an initramfs for a rootfs which means that after u-boot loads the zImage (and the dtb file) into memory, prior to kicking off the boot, the media is no longer needed.

(CASE: WORKING) If I place these files (zImage, dtb) on the MMC and boot from it (meaning zImage and dtb are initially loaded into memory from the MMC), then Linux is able to enumerate/read a USB stick in the USB2.0 OTG port.

(CASE: NOT-WORKING) If I place the same files (zImage, dtb) on a USB stick and boot from the USB stick (meaning this time they are loaded into memory from the USB stick), then Linux is unable to enumerate/read the USB stick in the USB2.0 OTG port. U-boot has no problem reading these files into memory prior to kicking off the boot process.

For the WORKING case the dmesg log shows ...

[ 3.253471] dwc2 ffb40000.usb: DWC OTG Controller

[ 3.258178] dwc2 ffb40000.usb: new USB bus registered, assigned bus number 1

[ 3.265229] dwc2 ffb40000.usb: irq 160, io mem 0x00000000

[ 3.270806] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002

[ 3.277580] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1

[ 3.284780] usb usb1: Product: DWC OTG Controller

[ 3.289463] usb usb1: Manufacturer: Linux 3.18.20PLAIN-USB dwc2_hsotg

[ 3.295884] usb usb1: SerialNumber: ffb40000.usb

[ 3.300904] hub 1-0:1.0: USB hub found

[ 3.304678] hub 1-0:1.0: 1 port detected

[ 3.308811] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver

[ 3.315385] usbcore: registered new interface driver uas

[ 3.320761] usbcore: registered new interface driver usb-storage

and then a little later:

[ 4.143425] usb 1-1: new high-speed USB device number 2 using dwc2

[ 4.253585] udevd[568]: starting version 182

[ 4.353988] usb 1-1: New USB device found, idVendor=18a5, idProduct=0304

[ 4.360690] usb 1-1: New USB device strings: Mfr=1, Product=2, SerialNumber=3

[ 4.367903] usb 1-1: Product: STORE N GO

[ 4.373613] usb 1-1: Manufacturer: Verbatim

[ 4.379696] usb 1-1: SerialNumber: 1208000000006A8D

[ 4.444049] usb-storage 1-1:1.0: USB Mass Storage device detected

[ 4.461279] scsi host0: usb-storage 1-1:1.0

For the NOT-WORKING case the dmesg log shows...

[ 3.273488] dwc2 ffb40000.usb: DWC OTG Controller

[ 3.278195] dwc2 ffb40000.usb: new USB bus registered, assigned bus number 1

[ 3.285245] dwc2 ffb40000.usb: irq 160, io mem 0x00000000

[ 3.290814] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002

[ 3.297587] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1

[ 3.304787] usb usb1: Product: DWC OTG Controller

[ 3.309470] usb usb1: Manufacturer: Linux 3.18.20PLAIN-USB dwc2_hsotg

[ 3.315889] usb usb1: SerialNumber: ffb40000.usb

[ 3.320903] hub 1-0:1.0: USB hub found

[ 3.324677] hub 1-0:1.0: 1 port detected

[ 3.328810] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver

[ 3.335384] usbcore: registered new interface driver uas

[ 3.340759] usbcore: registered new interface driver usb-storage

same as before, and then a little later:

[ 4.265500] udevd[567]: starting version 182

[ 4.393461] usb 1-1: new high-speed USB device number 2 using dwc2

[ 19.583374] usb 1-1: device descriptor read/64, error -110

udevd[567]: worker [576] timeout, kill it

udevd[567]: seq 529 '/devices/soc/ffb40000.usb/usb1' killed

[ 34.859798] random: dd urandom read with 42 bits of entropy available

[ 34.883443] usb 1-1: device descriptor read/64, error -110

[ 35.183449] usb 1-1: new high-speed USB device number 3 using dwc2

and then after booting is complete some more messages:

Poky (Yocto Project Reference Distro) 1.7.3 cyclone5 /dev/ttyS0

cyclone5 login: [ 50.373372] usb 1-1: device descriptor read/64, error -110

[ 65.673370] usb 1-1: device descriptor read/64, error -110

[ 65.973367] usb 1-1: new high-speed USB device number 4 using dwc2

[ 76.393373] usb 1-1: device not accepting address 4, error -110

[ 76.583368] usb 1-1: new high-speed USB device number 5 using dwc2

[ 87.003368] usb 1-1: device not accepting address 5, error -110

[ 87.009297] usb usb1-port1: unable to enumerate USB device

Can anybody out there shed some light on this behavior and what I can do to fix it?

I'll add that in u-boot I use the exact same bootcmd sequence, replacing the "mmc" loads with "usb" loads to memory.

bootcmd=run callscript;run mmcload;run bridge_enable_handoff;run mmcboot

usbbootcmd 'run callscript;run usbload;run bridge_enable_handoff;run usbboot'

Thanks in advance for insights out there!

George Broz
Moog Industrial Group

Files to be included for PCIe hard IP while synthesis

December 8, 2015, 8:13 pm

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I am using PCIe hard IP in my project... please let me know what all files I need to include while performing synthesis....