Nios Raw Ethernet

October 5, 2016, 1:09 pm

≫ Next: Pseudo Random Bit Sequence Verilog

≪ Previous: Assembler internal error Aria 10

We are looking for a closed loop network (daisy chain, ring network). Our network would consist of 7 10 boards with two Ethernet ports. We had an idea, but we are not sure if it would work. In reference to transmitting and receiving raw Ethernet frames using the Triple Speed Ethernet Core. The idea is this, to receive raw Ethernet frames via Port 1 (Ethernet Port 1) check if the frame is meant for a specific node process and forward the frame via Port 2 (Ethernet Port 2) etc..

Are there any examples that would control the Triple Speed Ethernet Core to receive and transmit raw Ethernet frames for Nios to handle?
Also, would there be anything that would help us out at the SoC level to help us with the above design?

We currently using the MAX 10 development kit and Quartus 16.0

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Pseudo Random Bit Sequence Verilog

October 5, 2016, 2:56 pm

≫ Next: Array Elements and Indexing

≪ Previous: Nios Raw Ethernet

Hi,

I want to send a pseudo random bit sequence down a sfp+ port on my Stratix V fpga. Unfortunately I am unfamiliar with verilog. Can anyone help me with this or point me to the right resources? Thanks!

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Array Elements and Indexing

October 5, 2016, 6:13 pm

≫ Next: error starting gdbserver

≪ Previous: Pseudo Random Bit Sequence Verilog

wire signed [11:0]cos;

x <= {{4{cos[11]}}

what is the operation done by " 4{cos[11]}" ?

is cos[11] multiplied by 4? i'm confused

please help !

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error starting gdbserver

October 5, 2016, 10:04 pm

≫ Next: Nios II 11.0 Software Build Tools for Eclipse question

≪ Previous: Array Elements and Indexing

Hi All

When I debug a project in Nios II Eclipse, there is an error: "error starting gdbserver". Can anyone solve this?

Thank You

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Nios II 11.0 Software Build Tools for Eclipse question

October 6, 2016, 12:22 am

≫ Next: How use EPF10K50ETI144 that not presented in supported devices

≪ Previous: error starting gdbserver

Hi All，
I want to use Nios II 11.0 Software Build Tools for Eclipse to create a new project, but in File->New, I cannot find this selection :Nios II Application andBSP from Template.

Whats the problem of this and if anybody know,pls help! Thank.

Attached Images

??.jpg (13.8 KB)

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How use EPF10K50ETI144 that not presented in supported devices

October 6, 2016, 12:42 am

≫ Next: reg [ x +: 12] mean ?

≪ Previous: Nios II 11.0 Software Build Tools for Eclipse question

I need use EPF10K50ETI144 , but this device is not presented in supported devices list in Quartus ii ver.8.
It have only EPF10K30ETI144 in FLEX10KE family. What should i do in this case?

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reg [ x +: 12] mean ?

October 6, 2016, 2:07 am

≫ Next: Does the fast output register ensure consistent timing?

≪ Previous: How use EPF10K50ETI144 that not presented in supported devices

what is the meaning of this syntax?

here x could be input vector

reg [ x +: 12]

please help !!

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Does the fast output register ensure consistent timing?

October 6, 2016, 2:32 am

≫ Next: Plsease urgent help in VHDL arrays

≪ Previous: reg [ x +: 12] mean ?

Hi,

I have some output pins in my FPGA design (actually bi-dir, should not matter) which connect to some external component in a modular system. The data rate on those pins is variable, and the actual delay from the FPGA to that external component is adjustable (using a programmable delay line IC).

Since everything is variable, I did not put any constraints into the SDC-file about these signals. I don't care about the delay. I can trim the delay line to ensure proper timing.

Now I just found out that the optimum delay line delay changes when I make changes to the FPGA design and re-synthesize it. Okay, I didn't think about that before, but it makes sense, as the launching register might be closer or farther away from the I/O pin. The problem is that I have to determine the optimum delay line value after each FPGA change.

My first idea was to come up with some bogus timing constraint, to enforce the fitter to at least generate the same timing (within some range, sure) for each synthesis. But I'm wondering if a better approach would be to just enable the fast output register option? I think I can rely on the clock distribution network inside the FPGA not to change, and I can expect the exact timing not to change as the output register is always at the same location.

Are those assumptions correct? What's your thought on this?

Note: I don't care about the exact timing, as long as it does not deviate too much after a re-synthesis (a few 100ps are accepted).

Best regards,
GooGooCluster

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Plsease urgent help in VHDL arrays

October 6, 2016, 3:54 am

≫ Next: red

≪ Previous: Does the fast output register ensure consistent timing?

red <= colour_schemes[{scheme,2'd3}][3:0]

this is a peace of verilog code n i wanna know how to do this in vhdl ?

note:

red is std_logic_vector(3 downto 0)
colour schemes is an array as follows

type colour_schemes is array(15 downto 0) of std_logic_vector(11 downto 0);
signal colour_schemes_array: colour_schemes;

please need help !!!

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red

October 6, 2016, 4:26 am

≫ Next: cannot simulate PLL ip

≪ Previous: Plsease urgent help in VHDL arrays

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cannot simulate PLL ip

October 6, 2016, 5:36 am

≫ Next: uart ip: can't get rx data

≪ Previous: red

Hi,

I try to use a PLL in my design. I successfully create it from Qsys.
Then i compile the files needed for simulation ( a vhd 'top level' file and a file called uart_pll_altera_iopll_151_m22pvxi.vo compiled in its own library).
When i try to simulate the design Modelsim-Altera complains about the uart_pll_altera_iopll_151_m22pvxi.vo file like this :

.....
uart_pll_altera_iopll_151_m22pvxi.vo(137): Instantiation of 'altera_pll' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /uart_pll/iopll_0
File: ../uart_pll/altera_iopll_151/sim/uart_pll_altera_iopll_151_m22pvxi.vo
# Searched libraries:
# ../uart_pll_altera_iopll_151

...

it looks like the generated file from quartus calls another component which canot be found....

anybody knows how to deal with it? should i include any primitive library ?

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uart ip: can't get rx data

October 6, 2016, 7:12 am

≫ Next: wire signed [10:-11]root3x_full; How do I implement this in VHDL?

≪ Previous: cannot simulate PLL ip

I generated an uart core from qsys and made a simulation with modelsim.
I instantiated two uart (one as transmitter and one as receiver); I connected the "uart_0_external_connection_txd" pin of the transmitter to the "uart_0_external_connection_rxd" pin of the receiver.
The uart transmitter seems work properly but I can't get the signal "uart_0_s1_dataavailable=1" from the receiver uart and the rxdata register is always 0.
Do you have any suggestion?
Thank for your help

Attached Images

modelsim_simulation.jpg (20.9 KB)

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wire signed [10:-11]root3x_full; How do I implement this in VHDL?

October 6, 2016, 9:10 am

≫ Next: Outputting a signal

≪ Previous: uart ip: can't get rx data

wire signed [10:-11]root3x_full; How do I implement this in VHDL?

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Outputting a signal

October 6, 2016, 2:53 pm

≫ Next: jtagserver authentication failure

≪ Previous: wire signed [10:-11]root3x_full; How do I implement this in VHDL?

Hi,

The Stratix V reference manuals says it has 1 SMA out for outputting clock signals. However I would like to use it for outputting a generated signal and sending it down a coaxial cable connected to the SMA. Is this possible? Thanks.

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jtagserver authentication failure

October 6, 2016, 2:58 pm

≫ Next: Quartus 13sp1 WEB ed: Functional /Timing Simulation do not work at all

≪ Previous: Outputting a signal

Hi All,

I have the Altera jtag server running as a service on windows 7 under user system, and I type the following commands to get remote access working. This has worked before, but I am almost ready to give on it now and physically move my chassis to another location.

On the jtag server host XXXX I type.

$ jtagconfig --enableremote somepassword

$ jtagserver.exe --status
Installed JTAG server is 'C:\altera\15.1\quartus\bin64\jtagserver.exe'
Server is running
Remote clients are disabled

I have tried restarting the windows service, and I also see the password datum updating in the windows registry when I change it ...

I had trouble getting the remote 13.1 jtag to work so I tried also upgrading the windows installation to 15.1.

On a Linux Red Hat 6 jtag client system, where we are still running altera 13.1, I type.

$ jtagconfig --addserver XXXX somepassword
$ jtagconfig
1) Remote server dugong: Authentication failure

Does the service on windows need to run in an account other than system, or possibly there is something else I am missing?

I doubt that this is a firewall issue as I can telnet to the Altera port on the windows and I see a connection with activity; many years ago I punched the proper holes in the windows firewall.

Thanks for any hints,

Jeff

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Quartus 13sp1 WEB ed: Functional /Timing Simulation do not work at all

October 6, 2016, 9:00 pm

≫ Next: Possible use transceiver as GPIO?

≪ Previous: jtagserver authentication failure

Hi all,
I'm a college student and is asked to use specific edition 13sp1 of quartus for VHDL design.
I run two computers on windows 10 and windows 8.1. For both PCs, when I click run the functional simulation, a separate small window pops up briefly and then closed automatically, but there is no following up window which suppose to show the simulation results.
I tried reinstall the software but it did not help.
Does this issue related to the version of my OS?
What should I do to make it work?

Thanks!

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Possible use transceiver as GPIO?

October 6, 2016, 10:23 pm

≫ Next: Nios to Avalon signals

≪ Previous: Quartus 13sp1 WEB ed: Functional /Timing Simulation do not work at all

Hello,

Is it possible to use the LVDS transceiver IO as GPIO or are they dedicated as LVDS?

I have searched all day and found nothing definitive.

I tried to use as GPIO but I get:

Error (169033): I/O pin counter[0] with Termination logic option setting Series 50 Ohm without Calibration cannot be placed inside I/O Bank B0L because the I/O bank does not support the requested Termination setting

Thanks, Tom

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Nios to Avalon signals

October 7, 2016, 7:02 am

≫ Next: Installing Altera OpenCL on Windows 10

≪ Previous: Possible use transceiver as GPIO?

Hi,

My background is VHDL and I am now working with the NIOS processor. I have a Modified simple socket server design witch the IP address and MAC address are written in hard code. I would like to export these signal to the avalon world or out of QSYS so I can store a value in either FPGA registers or and external EEPROM. could some one lead me into the right direction with how this is done. My knowledge of C code is very minimal.

the files I m editing are the Simple_socket_server.H and Network_utilities.C files

Code:

error_t get_board_mac_addr(unsigned char mac_addr[6])

{

    error_t error = 0;

    alt_u32 signature;

    

    /* This last_flash_sector region of flash is examined to see if 

     * valid network settings are present, indicated by a signature of 0x00005afe at 

     * the first address of the last flash sector.  This hex value is chosen as the 

     * signature since it looks like the english word "SAFE", meaning that it is 

     * safe to use these network address values.  

    */

  

    mac_addr[0] = 0x00;

 mac_addr[1] = 0x07;

 mac_addr[2] = 0xed;

 mac_addr[3] = 0x12;

 mac_addr[4] = 0x8f;

 mac_addr[5] = 0xff;

    if (!error)

    {

        printf("Your Ethernet MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n", 

            mac_addr[0],

            mac_addr[1],

            mac_addr[2],

            mac_addr[3],

            mac_addr[4],

            mac_addr[5]);

    

    }

    

    return error;

Code:

#define IPADDR0   192

#define IPADDR1   168

#define IPADDR2   1

#define IPADDR3   234



#define GWADDR0   192

#define GWADDR1   168

#define GWADDR2   1

#define GWADDR3   1

#define MSKADDR0  255

#define MSKADDR1  255

#define MSKADDR2  255

#define MSKADDR3  0

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Installing Altera OpenCL on Windows 10

October 7, 2016, 8:36 am

≫ Next: Show delays of path in chip planner

≪ Previous: Nios to Avalon signals

Making attempt to expand OpenCL experience to FPGAs. Most intrigued by the whole idea. Followed https://documentation.altera.com/#/00016207-AA$NT00067078 hoping to use the Altera OpenCL API. Followed all installation steps on my Windows 10 machine, as I understand them. No installation dialog appeared. setup.bat and setup_pro.bat simply run without comment. There is no indication where anything was installed, if anything was installed at all.

Doing due-diligence, I searched in obvious places for files to no avail. Also searched https://www.youtube.com/user/alterac...h?query=opencl for their OpenCL videos. There is no "Part 1" for Getting Started with OpenCL, which would presumably explain windows installation.

Surely, I am missing something. Many thanks for whatever advice can be offered.

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Show delays of path in chip planner

October 7, 2016, 8:39 am

≫ Next: load .mif-file on DE0-CV board

≪ Previous: Installing Altera OpenCL on Windows 10

Hi,

In the Chip Planner, I use "Generate Fan-In/Out Connections" to figure out the connection between two related nodes (lut, or register). But I can't see the delay between them, for example, from one lut to another lut. The "Show Dealys" button doesn't make any difference.

The quartus edition that I use are 11.0, 13.1, 15.1. And the FPGA is EP4CE115F29I7N. Is there something that I missed? Or, are there any other ways to help me get the delay?

Thank you!

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