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Question about Audio port

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Hi altera forum.
Could i ask you about Audio port operation?

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#include "address_map_nios2.h"
#include "stdlib.h"
#include "stdio.h"


#define BUF_SIZE 500000


#define AUDIO_SUBSYSTEM_AUDIO_BASE 0xFF203040;


volatile int * audio_ptr = (int *) AUDIO_SUBSYSTEM_AUDIO_BASE; // audio port address


int fifospace = 0;
int buffer_index=0;
int left_buffer[BUF_SIZE];
int right_buffer[BUF_SIZE];


int main(void)
{
volatile int *audio_ptr = (int *) AUDIO_SUBSYSTEM_AUDIO_BASE; // audio port address
*audio_ptr = 0x03;
int wi=0;
FILE * fpi1 = fopen("01_explosion.raw", "rb"); // get file at project file

while(1){
wi = ((*audio_ptr)&0x200)>>9; // WI


fread((void*)left_buffer,172000,sizeof(float),fpi1 ); // read file and store to left_buf, file size 172KB

if(wi==1)
{
buffer_index=0;
while(buffer_index < BUF_SIZE)
{
*(audio_ptr + 3) = left_buffer[buffer_index];
*(audio_ptr + 2) = left_buffer[buffer_index];
++buffer_index;

wi=(((*audio_ptr)&0x200)>>9);
if(wi==0) //wait until next sampling
{
while(wi==0){wi=(((*audio_ptr)&0x200)>>9);}
}

}

}
}
}

--------------------------------------------------------------
i'm trying to get audio file from project file and to play through the speaker with monitor program.
but it is not play correctly, but sounds like radio signaling sound.
my raw file is 32-bit, mono, format=raw, and 48K sampling.

what should i do?

Programming problems with VMware and Windows 10

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I am currently working on a project with a Cyclone IV E. I use Quartus Prime version 16.1.0 on a desktop Windows 7 64-bit machine and use a USB Blaster rev. B for programming and debug. Everything works just fine.

In order to be able to program and debug at the installation location, I have installed the development system on Windows 10 64-bit running under VMware Fusion on a MacBook Pro. With this setup, everything works fine as well, except programming. When I try to program the device with the Quartus programmer, I get the following error messages:

209040 Can't access JTAG chain
209012 Operation failed

Programming the same target board with the same programmer works perfectly from my desktop PC.

A logic analyzer shows identical signal patterns on the JTAG interface.

Running the JTAG Chain Debugger gives the following error messages:

Error: JTAG chain problem detected
Error: TDI connection to the first detected device UNKNOWN_NO_JTAG_ID might be shorted to GND
Error: The TCK and TMS conections to the device before the first detected device UNKNOWN_NO_JTAG_ID might have a problem

Both systems use the same device driver (2.12.0.0) for the Altera USB-Blaster, and I experience exactly the same problem with a Terasic USB-Blaster.

Does anyone have an idea what may be causing this? Is this a Windows 10 or a VMware problem?

Regards

Erik

8 SPI Master to be used in Cyclone V 5CSXFC5C6

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We need to support 8 SPI slave device i.e. we Need 8 SPI - 4 wire Master signals for our support.
We don't want to control our 8 SPI slave device with CS (Chip select), we need 8 separate SPI 4-wire signals.

In Cyclone V we have only 2 SPI Master signals with 2 CS.

My question is that whether we can assign any FPGA GPIO as SPI signals (SPI_CLK, SPI_MOSI, SPI_MISO) and whether we can use SPI IP Core for the GPIO we have selected.

set_max_delay vs set_net_delay

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Hi,

I haven't understood clearly the difference between set_max_delay and set_net_delay and the use case in constraining the design.
What I can understand from the quartushelp is that the only difference between set_max_delay and set_net_delay is that, max and min value can be set using set_net_delay whereas only max constraint can be provided using set_max_delay.

Problems enabling hps2fpga & lwhps2fpga bridges

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The problem:
When trying to enable either the hps2fpga or the lwhps2fpga bridge in Linux, the Linux system locks up.

From the rocketboards example:
Command used: "echo 1 > /sys/class/fpga-bridge/hps2fpga/enable"
*or*
Command used: "echo 1 > /sys/class/fpga-bridge/lwhps2fpga/enable"

Other useful information:
-The FPGA is configured with a validated .rbf (and indicates in "user mode" per /sys/class/fpga/fpga0/status)
-The fpga2hps bridge can be enabled/disabled normally.
-The issue has appeared after we switched Linux versions and the configurator from Yocto to Buildroot
-If the FPGA is configured with the .rbf and a reboot command issued, the bridges are up once Linux boots and our system functions normally. *unless we try to bring down the hps2fpga/lwhps2fpga bridges

The issue in question has appeared since we switched our Linux environment. There is a high probability that we have missed a configuration setting that would be needed to properly perform this action - any suggestions on this front would be highly welcome.

Not sure if it is helpful or not, the version from /etc/os-release indicates 2015.08-git.

Thank you in advance for any assistance.




10G Low Latency MAC CRC Errors

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Good Day,
I am attempting to use Altera's Low Latency MAC and Arria 10 Transceiver Native PHY to stream data from an Arris 10. The Ethernet CRC at the end of the packet is intermittently incorrect according to my PC's NIC. The MAC inserts the CRC into the packet before sending it to the PHY.
I'm not sure what is going wrong with the CRC or the calculation but the problem is not completely predicable. I'm equally at a loss of what the error is and how to debug it with out a deep dive into CRC-32 calculations.
Any suggestions on how to fix or research the problem would be appreciated.

AOCL BLAS support

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Hello,

There's a post from last year on the forum about BLAS support from ImpulseC (see http://www.alteraforum.com/forum/showthread.php?t=47549), but I haven't seen any newer information specifically from Altera/Intel.

We would be interested in using BLAS SGEMM and DGEMM calls with Altera OpenCL for a few local applications we have. Is there any plan to include this support in future releases of Altera OpenCL compilers?

Thanks,
Jeff

Add a custom instruction with only one input - BSP auto generated

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I've just created a custom instruction in Qsys that uses only one input. There is only dataa[] in the interface.

However the Eclipse generates a instruction with 2 operands.

Code:

#define ALT_CI_WELLPRNG_0(A,B) __builtin_custom_inii(ALT_CI_WELLPRNG_0_N,(A),(B))
Did I do anything wrong? Or should I always fix that by hand?

Thank you.

LEON3 on DE2 board - LCD display apblcd.h file needed - Hitachi HD44780

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I am trying to use the LCD display on the Cyclone II DE2 board by using the LEON3 processor. According to the template design written by students (link below), they wrote apblcd.h and apblcd.c files o aid using their apblcd.vhd core. Does anyone have these files? I do not know C but would like to try to get the LCD to work on the LEON3 so these files would be very helpful.

Thanks!

http://publications.lib.chalmers.se/...ext/146808.pdf

Quartus Error (13066): Illegal directional connection from the pin (inout)

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Hello all,
I've posted this question to VHDL board, please forgive me if you've seen it there. Just thought it could be Quartus related so repost it here again.

I'm using Quartus 16 lite to create a simple interface between FT2232H and DE0-Nano in synchronous FIFO mode.
Please see simplified code below.

Code:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--use IEEE.STD_LOGIC_UNSIGNED.all; -- for some old compiler
use IEEE.MATH_REAL.all;


library altera;
use altera.altera_primitives_components.all;
entity Tester is
    port(
                --DE0-Nano signal/pin definition
);
end entity

COMPONENT PLL IS
    PORT
    (
        ---
    );
END COMPONENT;

COMPONENT FIFO IS
    PORT
    (
        ---
    );
END COMPONENT;

COMPONENT Counter IS
    PORT
    (
        ---
    );
END COMPONENT;


ARCHITECTURE SYN OF Tester IS

signal  in_aclr, PLL_areset:    STD_LOGIC;
signal  fast_clk, FT2232_clk: STD_LOGIC ;        --PLL clock and FT2232H Sync FIFO mode clock
signal  nRXF, nTXE, nWR, nRD, nOE: STD_LOGIC;  -- FT2232H interface signals
signal  FT_DataBus, iBusData_IN,iBusData_OUT, iData : STD_LOGIC_VECTOR (7 DOWNTO 0);    --Databus and its derivatives
signal  ........................    -- other signal

begin


        PLL_areset <= not GPIO_2_IN(0);
        in_aclr <= GPIO_2_IN(0) and iPLL_locked;
       
        FT2232_clk <= GPIO_0_IN(0);
        nRXF <= GPIO_0(5);
        nTXE <= GPIO_0(7);
        GPIO_0(3) <= nWR;
        GPIO_0(1) <= nRD;
        GPIO_0(0) <= nOE;
        FT_DataBus <= (GPIO_0(8), GPIO_0(9),  GPIO_0(10), GPIO_0(11),GPIO_0(12),GPIO_0(13),GPIO_0(14), GPIO_0(15));


--        process (nOE)
--        begin
--            if nOE = '0' then
--                iBusData_IN <= FT_DataBus;
--                FT_DataBus <= (others => 'Z');
--            else
----                iBusData_IN <= (others => '0');
--                FT_DataBus <= iBusData_OUT;
--            end if;
--           
--        end process;


        Process (in_aclr, FT2232_clk)
        begin
            if in_aclr = '0' then
                iBusData_IN <= (others => '0');
            elsif rising_edge(FT2232_clk) then
                iBusData_IN <= FT_DataBus;
            end if;
        end process;


        FT_DataBus <= iBusData_OUT when nOE ='1' else (others => 'Z');

--------
Mapping components
---------

When I tried to compile it, I got these error message "Error (13066): Illegal directional connection from the pin "GPIO_0[8]" to the node "iBusData_IN[7]" for all 8 bits.
Searched around and tried a few methods but never solve it. Can't figure out why? Is it because some new development of VHDL I'm not aware or just the Quartus' interpretation?
Since it should be very simple and straight forward, seems Quarts doesn't like me to use inout pin the feed a internal logic cell, but the bidir has to be supported because it's one of fundamental design units.
Maybe I misunderstand either VHDL or Quartus error message ( humbly thinking altera could make the message more clear).
Anyway, please help and your help is appreciated in advance.

Thanks,
Yu

Timing Corner

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Hi,

I am working on timing closure of a design.
I have the following question:
Is there a way I can indicate the tool to optimize timing for all the corners or for a specific corner? My design seems to be ok with timing at the two end corners (Fast and low temperature; Slow and high temperature). However, it seems to be failing for slow-low temperature. Going by this post (https://www.altera.com/support/suppo...22009_205.html), the tool does not optimize timing for slow-low temperature corner. Is there a solution for this?

Thanks,
Vittal

"Fatal Error: Segment Violation at 0x10" during Synthesis

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Hi,

I'm getting following error when I try to Synthesize my design. Any help to fix this will be very helpful. Quartus tool version - Quartus Prime Pro 16.1.0


*** Fatal Error: Segment Violation at 0x10 24047 Module: quartus_syn 24048 Stack Trace:
24049 0x38fcb6: VRFX_SGATE::create_ram_instances() + 0x42c (synth_vrfx2)
24050 0x39aa8e: VRFX_SGATE::convert_netlist() + 0x722 (synth_vrfx2)
24051 0x3a701d: new_verific::VRFX2_EXTRACTOR::extract_hierarchy(ch ar const*, BASEX_ELABORATE_INFO*, bool, bool) + 0xe3 (synth_vrfx2)
24052 0x65ec4: QIS_RTL_STAGE::IMPL::elaborate_verific(QHD_PARTITI ON&, HDB_ENTITY*, HDB_MODEL*, BASEX_ELAB_INFO_CORE&) + 0xba (synth_qis)
24053 0x84be1: QIS_RTL_STAGE::IMPL::elaborate(QHD_PARTITION&) + 0x75f (synth_qis)
24054 0x85950: QIS_RTL_STAGE::elaborate(QHD_PARTITION&) + 0xc (synth_qis)
24055 0x85a6a: QIS_RTL_RECURSIVE_ELABORATION::after_elaboration(Q HD_PARTITION&) + 0x114 (synth_qis)
24056 0x85138: QIS_RTL_STAGE::IMPL::elaborate(QHD_PARTITION&) + 0xcb6 (synth_qis)
24057 0x85950: QIS_RTL_STAGE::elaborate(QHD_PARTITION&) + 0xc (synth_qis)
24058 0x85a6a: QIS_RTL_RECURSIVE_ELABORATION::after_elaboration(Q HD_PARTITION&) + 0x114 (synth_qis)
24059 0x85138: QIS_RTL_STAGE::IMPL::elaborate(QHD_PARTITION&) + 0xcb6 (synth_qis)
24060 0x85950: QIS_RTL_STAGE::elaborate(QHD_PARTITION&) + 0xc (synth_qis)
24061 0x85a6a: QIS_RTL_RECURSIVE_ELABORATION::after_elaboration(Q HD_PARTITION&) + 0x114 (synth_qis)
24062 0x85138: QIS_RTL_STAGE::IMPL::elaborate(QHD_PARTITION&) + 0xcb6 (synth_qis)
24063 0x85950: QIS_RTL_STAGE::elaborate(QHD_PARTITION&) + 0xc (synth_qis)
24064 0x85a6a: QIS_RTL_RECURSIVE_ELABORATION::after_elaboration(Q HD_PARTITION&) + 0x114 (synth_qis)
24065 0x85138: QIS_RTL_STAGE::IMPL::elaborate(QHD_PARTITION&) + 0xcb6 (synth_qis)
24066 0x85950: QIS_RTL_STAGE::elaborate(QHD_PARTITION&) + 0xc (synth_qis)
24067 0x55ecf: qis_elaborate + 0x168 (synth_qis)
24068 0x51ec7: TclNRRunCallbacks + 0x47 (tcl8.6)
24069 0x536e7: TclEvalEx + 0x947 (tcl8.6)
24070 0xfb366: Tcl_FSEvalFileEx + 0x266 (tcl8.6)
24071 0xfb47e: Tcl_EvalFile + 0x2e (tcl8.6)
24072 0x11ebc: qexe_evaluate_tcl_script(std::string const&) + 0x382 (comp_qexe)
24073 0x18dcf: qexe_do_tcl(QEXE_FRAMEWORK*, std::string const&, std::string const&, std::list<std::string, std::allocator<std::string> > const&, bool, bool) + 0x597 (comp_qexe)
24074 0x19d7b: qexe_run_tcl_option(QEXE_FRAMEWORK*, char const*, std::list<std::string, std::allocator<std::string> >*, bool) + 0x57e (comp_qexe)
24075 0x3e06a: qcu_run_tcl_option(QCU_FRAMEWORK*, char const*, std::list<std::string, std::allocator<std::string> >*, bool) + 0x1065 (comp_qcu)
24076 0x74f2: qsyn2_tcl_process_default_flow_option(ACF_VARIABLE _TYPE_ENUM, char const*) + 0x72 (quartus_syn)
24077 0x1c586: qexe_standard_main(QEXE_FRAMEWORK*, QEXE_OPTION_DEFINITION const**, int, char const**) + 0x6b3 (comp_qexe)
24078 0x6017: qsyn2_main(int, char const**) + 0x137 (quartus_syn)
24079 0x407e0: msg_main_thread(void*) + 0x10 (ccl_msg)
24080 0x602c: thr_final_wrapper + 0xc (ccl_thr)
24081 0x4089f: msg_thread_wrapper(void* (*)(void*), void*) + 0x62 (ccl_msg)
24082 0xa559: mem_thread_wrapper(void* (*)(void*), void*) + 0x99 (ccl_mem)
24083 0x8f92: err_thread_wrapper(void* (*)(void*), void*) + 0x27 (ccl_err)
24084 0x63f2: thr_thread_wrapper + 0x15 (ccl_thr)
24085 0x42c37: msg_exe_main(int, char const**, int (*)(int, char const**)) + 0xa3 (ccl_msg)
24086 0x647a: main + 0x26 (quartus_syn)
24087 0x1ec36: __libc_start_main + 0xe6 (c.so.6)
24088
24089
24090 End-trace

Thanks,
pcs

ALtera MAX10 JTAG Problem

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Hello,
I made some BLDC and IO expander boards based on Altera MAX10, and i have strange problem that from Quartus at first programming after power was supplied, it does not want to program, but second time and for the rest of debugging session, it works first time (I.E just first JTAG sessionis failing, rest of them working every time without fail) . This is very strange behavior i noticed with all of my MAX10 Boards.

What pushed me to make this thread is that new boards that i made take this effect to the next level. From second try to 20-30 tries Altera does not want to be programmed, but then again, just then i get first successful code loaded to FPGA (just to Altera, not to internal flash so it can boot on it's own) it start to work as it should, every other data loading to MAX10 works from that moment on, until next power-up.

Any idea why it can be happening ?

This is my JTAG for MAX10.
Attached Images

OpenCV with Nios II under windows 7

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Hello,
I am trying to use OpenCV with Nios II under windows but when I build my project, it seems like if Nios II does not know the OpenCV library. How can I include this library within my Nios II project?
Thank you very much

Build de0-nano-soc with web license?

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I have a cyclone V de0-nano-soc from terasic. I have successfully built a standalone (no SOC) vhdl project with and with out nios II. All of this was done on the 13.1 web version of quartus. When I try to replace the nios II core with the built in soc arm core, quartus produces a time_limited.sof which is useless. Is there a way to build the soc on the terasic nano with the web license?

How to access memory with Custom IP?

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Hello,
I have a working example which reads image data from host PC transfer it to an FPGA using PCIe which store in memory then a frame reader is used to show the image on a vga screen.
I have developed a custom entity which has to make calculations to the data stored in memory. The question is, as i am beginner here, how can I access the image data in the memory so I can make the calculation then I can re-save the data in the memory before it is shown again on the VGA screen.
The developing board is de2i-150.

Thank you in advanced,

Albar

Altera DE-1: "Error: Can't recognize silicone ID for device 1"

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Dear fellow Forum Users,

I am struggling to flash a POF to my brand new DE-1. I can connect to the device via the control panel app, I can flash binaries to the memory from there, I can flash a SOF to the DE-1 via Quartus in JTAG mode, but whenever I try to switch to "Active Serial Programming" mode, and flash a POF, I get the message "Error: Can't recognize silicon ID for device 1".

I have followed the various threads on this topic, and have tried the solutions described in there, without success. What I have done by now:

- Try different USB cables and USB ports (both directly on the PCs motherboard, as well as via an active USB hub)
- Try different versions of Quartus (13 and 16.1), both with the same results
- Try different OS (Win 10 64bit, Win 7 32 bit via Virtualbox, native Linux Quartus on Ubuntu 16.04), all with the same results

The device is also autodetected when using the corresponding button in Quartus' programmer popup, however, I am greeted with the following popup when using it:

"Encounter devices with shared JTAG header for device 1. Please select your device: [] EP2C15 [] EP2C20"
(see screenshot at http://www.kersch.at/quartus.png )

I have not connected another FPGA or JTAG enabled device to this PC.

Any suggestions on how to proceed? Thanks for your support!

Martin

HDMI IP error

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when i use the hdmi ip ,the follow error accur,what does it mean?
Error (114006): Database file d:/altera/16.0/quartus/common/devinfo/20nm/nightfury5/ddb_nightfury5_crosstalk.ddb, created by Quartus Prime Version 16.0.0 Build 211 04/27/2016 SJ Standard Edition software, not compatible with current Quartus Prime Version 16.0.1 Build 218 06/01/2016 SJ Standard Edition software

Cyclone V SOC and B-LVDS

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Hello all,

I would like to ask you if anyone have tried to use B-LVDS connection between Cyclone V and Cyclone IV. If yes how did you connect it and how did you make termination.

Many thanks for help

Arria 10 SOC Virtual Platform Uart Modelling

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Hi,

I am using Arria 10 SoC Virtual platform on linux platform. I simply want to test uart in virtual platform. I have written a simple code to read a register of UART(to be specific line control register(RO)). Then cross complied it to a .out format. Then copied it to the target platform and tried to run the .out file. But i am getting and error which shows segmentation error.

Kindly help me to solve this issue.

Thanks in advance

Regards
krish
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