Quantcast
Channel: Altera Forums
Viewing all 19390 articles
Browse latest View live
↧

Generate Case Instantiation

January 20, 2017, 6:49 am
$
0
0
Hi,

I would like to instantiate a parameterized sub-module "test1" based on an input value SW[6:0]. So I implement a generate case structure as follows:

always @(*) begin
generate
case (SW[6:0])
7'b0000000: begin
test1 t1(.a(SW[6:0]), .b(LEDR[17:6]));
defparam t1.NUM_PULSE = 1;
defparam t1.SAMPLES_PER_CYCLE = 8;
end
7'b0000001: begin
test1 t1(.a(SW[6:0]), .b(LEDR[17:6]));
defparam t1.NUM_PULSE = 1;
defparam t1.SAMPLES_PER_CYCLE = 16;
end
default: begin
test1 t1(.a(SW[6:0]), .b(LEDR[17:6]));
defparam t1.NUM_PULSE = 1;
defparam t1.SAMPLES_PER_CYCLE = 8;
end
endcase
endgenerate
end

But the Altera gives me the following errors:

Error (10170): Verilog HDL syntax error at Correlation.v(74) near text "generate"; expecting "end"
Error (10170): Verilog HDL syntax error at Correlation.v(77) near text "("; expecting ";"
Error (10170): Verilog HDL syntax error at Correlation.v(79) near text "defparam"; expecting "end"
Error (10170): Verilog HDL syntax error at Correlation.v(82) near text "("; expecting ";"
Error (10170): Verilog HDL syntax error at Correlation.v(84) near text "defparam"; expecting "end"
Error (10170): Verilog HDL syntax error at Correlation.v(87) near text "("; expecting ";"
Error (10170): Verilog HDL syntax error at Correlation.v(89) near text "defparam"; expecting "end"
Error (10170): Verilog HDL syntax error at Correlation.v(92) near text "endgenerate"; expecting "end"
Error (10112): Ignored design unit "Correlation" at Correlation.v(7) due to previous errors

Can any of you gives me some hints on what causes this compilation error?

Thanks

-Roger
↧
Search

Quartus and Modelsim add libraries automatically

January 20, 2017, 9:04 am
$
0
0
Is there a way to have quartus automatically include the libraries I need in modelsim? Each time I'm manually adding altera_mf_ver for example when I launch modelsim from quartus.

Thank you
↧
↧

Is it possible to connect two ethernet DE2-115 PHY chips back to back?

January 20, 2017, 10:56 pm
$
0
0
I have a DE2-115 board, and I want to connect two ethernet PHY chip back to back by using Media-Independent Interface (MII) (to work as a simple forwarder). I've been trying to connect MII pinouts with verilog code below, just to find that the ethernet is detected but I can't ping or connected to internet. I've also made sure that my ethernet cable works perfectly (ping and internet) by directly connect it to my laptop.

How to correctly connect ethernet PHY chips?

Thank you,

rosmianto
Attached Files
↧

FPGA configuration and Nios-II application software into the EPCS

January 21, 2017, 2:25 am
$
0
0
Hi,

I have the design where i have FPGA logic interfacing with Nios-II. I used Quartus Prime 16.1 Standard Edition. I used Cyclone-IV Device EP4CE55.

I want to put the FPGA configuration and Nios-II application software into the EPCS without using EPCS Controller in Qsys. Is there any method to do?

Thanks in advance

Regards,
Nandish Jasani.

↧

University license for OpenCL?

January 21, 2017, 3:53 am
$
0
0
Hello,

I'm trying to follow the introduction to OpenCL videos (https://www.youtube.com/watch?v=4PUKzI14mLY) but I'm currently stuck when trying to compile OpenCL for my board:
Code:
aoc device/vector_add.cl -o bin/vector_add.aocx --report
aoc: Selected default target board s5_ref                       
/home/renagen/opt/intelFPGA/16.1/opencl_example_vector_soc/vector_add/device/vector_add.cl:23:48: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance
__kernel void vector_add(__global const float *x,
                                              ^
/home/renagen/opt/intelFPGA/16.1/opencl_example_vector_soc/vector_add/device/vector_add.cl:24:48: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance
                        __global const float *y,
                                              ^
2 warnings generated.
Could not acquire a valid license for the Intel(R) FPGA SDK for OpenCL(TM).
Error: Verilog generator FAILED.
Refer to vector_add/vector_add.log for details.
The LM_LICENSE_FILE is pointing to my license file which contains:
Code:
# Altera SDK for OpenCL (University), 1 Seat(s)
# - Maintenance Expiration of 2018.01
Have you ever experienced such kind of error?
Does anyone know if the University license is compatible for such use?

Thanks.
↧
↧

"14736 ERROR: Cannot find sequencer/sequencer.elf" on Lite 16.1 -- how to debug?

January 21, 2017, 12:18 pm
$
0
0
Hello,

The EMI megawizard gives the aforementioned error while trying to generate "altera_mem_if_lpddr2_emif".
Using Quartus Prime Lite 16.1 on an unsupported Linux amd64 distribution. Here's the various env settings I have tried:

Code:
wmname LG3D

export PATH=$PATH:/opt/alt/16.1/modelsim_ase/linux:/opt/alt/16.1/quartus/bin

export QSYS_ROOTDIR=/opt/alt/16.1/quartus/sopc_builder/bin
export QUARTUS_ROOTDIR=/opt/alt/16.1/quartus
export SOPC_KIT_NIOS2=/opt/alt/16.1/nios2eds

export TEMP=/tmp
export TMP=/tmp
After trying to tackle this for a few days, I am now out of ideas. Looking for any suggestions how to debug the complex java/Tcl maze and find out what is it that I am missing - a library, an env setting, or something else.

I have the suspicion that the NIOS part of the IP generation is failing, so it could be something with the EDS, but I have no prior experience with EDS at all. The synthesis/fit/programming portions of Quartus behave as expected.
↧

Max10 UFM Initialization

January 21, 2017, 1:51 pm
$
0
0
I'm a beginner. I have a Max10 Eval board and am working on interfacing to the UFM. I'm having an issue with troubleshooting and thought if I could initialize a value I could at least try to read it back as a first step. Would Quartus' IN-System Memory Editor work to initialize the IP or will I have to create my own .hex file? The formatting is a little cumbersome, so I'd like to at least have some known values in the flash and not take the chance that my initialization failed without me knowing.
↧

How to know what files to include in Nios II main file?

January 21, 2017, 5:06 pm
$
0
0
When I initially created a system with just a JTAG UART as peripheral and then chose "Nios II application and BSP from template" and then selected small hello world, the .c file with the main routine contained only 1 header file:

#include "sys/alt_stdio.h"

I assume that this contains the printf function used for hello world application. However, I do not find a folder named sys anywhere in the things generated by the Nios II Eclipse IDE.

Anyway, when I later add more peripherals like PIO to my design and regenerate the SOPC file, how do I know what header files to include so I can use the new peripherals? Also, where are the HAL version of IORD and IORW declared for the new peripherals like the PIO?
↧
Search

Configuration Cyclone V 5CEBA9F23C8N

January 21, 2017, 11:49 pm
$
0
0
I Design Board With 5CEBA9F23C8N
I choose AS Configuration for programming & EPCS128
After Develop PCB I start to program my board

STEP1- Compile My Design in quartus 16.1(SIMPLE LED ON FOR TESTING)
STEP2-CONVERT .SOF FILE TO .POF (FOR ACTIVE SERIAL EPCS128)
STEP3-PROGRAM EPCS128 VIA PROGRAMMING(I SELECT ACTIVE MODE)
STEP4- SUCESSFULLY EPCS128 PROGRAM
But my fpga didn’t program L
So I check every pin realated to fpga and epcs128 for programming
Every pin is work fine except nstatus and dclk
Nstatus stay in low alltime & dclk didn’t have clock
I think the fpga stay in POR but I didn’t find out reason
Anyone knows whats reason?
(I have experience for design fpga board with max10 but max10 have internal flash & this my first experience with epcs128)
↧
↧

Unconstrained clock inside J2A Master?

January 22, 2017, 10:01 am
$
0
0
For some reason, I'm getting this as an unconstrained clock inside the JTAG to Avalon master bridge I'm using in Qsys for System Console access:

u_flash_control|j2a_master|j2a_master|transacto|p2 m|address[10]

Why would an address signal inside an IP be considered as an unconstrained base clock? It doesn't seem to affect my design.
↧

Multistage pipelined multiplexer

January 22, 2017, 11:36 am
$
0
0
Hello,

My design has to switch between four - 128 bit wide buses.
Using a simple coded mux (even with registered inputs and outputs) causes Fmax to drop to unacceptable levels.

I'm thinking to use a multistage pipelined MUX. I.E: the input buses will themselves be broken into smaller pipelined segments.
Does the IP catalog provide such a component ? Can the LPM_MUX be configured in such a way ?
↧

What exactly is this thing called Nios II (Classic) processor?

January 22, 2017, 11:36 am
$
0
0
In the Qsys in Quartus Prime 16.1 Lite, I have found Nios II (Classic) processor and another entry of a component without the word Classic in it.

What exactly is this Nios II Classic processor and why should it not be used for newer designs?
↧

SDI over IP

January 22, 2017, 1:18 pm
$
0
0
Hi
I have already designed and implemented TS over IP (SMPTE-2022-1/2) using Altera FPGAs, 1G Ethernet and external DDR-2 memory. I want to start design and implementation of 3G-SDI over IP (SMPTE-2022-5/6) using 10G MAC.
Has anybody a similar experience with SDI over IP? How much it is different? Is it more difficult (besides 10G MAC)?

Thanks
↧
↧

a way to keep the program when FPGA is disconnected from the USB blaster

January 22, 2017, 4:56 pm
$
0
0
Hello,

I was wondering if there is a way to keep the program when FPGA is disconnected from the USB blaster?
I am working with DE2 and DE0 boards..

I tried with Active Serial Mode Programming, but it is only useful to keep the program when FPGA is disconnected from the power supply

Thank you
↧

Setting VCC on MAX 10

January 22, 2017, 7:20 pm
$
0
0
An old VHDL design is being ported to a MAX 10 device (10M2DCU324C8G). It is to run in a 3.3V system. The Quartus Prime Lite compiled it and assigned pins but it configured all the pins to 2.5V (default). Where does one specify the VCCIO voltage so that it will assign all pins to a 3.3V type (LVCMOS seems to be the right one).
I tried to use "assignments->settings->operating voltages and conditions->Voltage" but all values are grayed and can not be changed.
↧
Search

Can the Cyclone V's FPGA handle a 1 Gigabit long shift register?

January 22, 2017, 10:05 pm
$
0
0
I've been studying Verilog for about a week now moving from c/c++,
but was wondering if something like this was possible to create a
shift register that was 1 Gigabit long?

Double checking before sending it over USB Blaster II for the board's very first project.

I updated an example Intel/Altera had posted for a serial in serial out
with a clock and shift enable. Here is the change I made:

module Gigabit_Shift_Register(clk,
shift,
sr_in,
sr_out,
);

input clk, shift;
input sr_in;
output sr_out;

reg [999999999:0] sr;

always@(posedge clk)
begin
if (shift == 1'b1)
begin
sr[999999999:1] <= sr[999999998:0];
sr[0] <= sr_in;
end
end

assign sr_out = sr[999999999];

endmodule
↧

Can .RBF Raw Binary be run natively from power on from SPI flash?

January 22, 2017, 10:34 pm
$
0
0
Hi All,

While being new to the whole Quartus thing, I was wondering if it is possible to run a raw binary .RBF from SPI Flash natively by HPS without Uboot or any OS loaded.

Are the .RBF's the bare metal binaries for Arm Cortex A9?

Can Quartus make executable ARM Cortex A9 binaries?

And the last thing I was wondering is if we can use .SOF files natively as well.

I was also reading that the ARM Cortex also comes in MCU form with onboard flash ARM Cortex M9.
This would be fun to explore, along with the third type of ARM Cortex which I forget how it loads.

Thank you for your help.
↧
↧

DE10-Lite System Builder

January 21, 2017, 2:37 pm
$
0
0
Trying to get a zero warning build of a simple project generated by the Terasic System Builder for a minimal system..

Just the clocks and the LEDRs and the Switches.
1) Generate the project, then double click on .qpf file in the CodeGenerated/DE10_Lite/ folder.
2) To eliminate the no project file defined, add the *.v file to the current project, add/remove files to project and select the .v file.
2) To eliminate a warning on the number of processors being used by the software, select the Compilation Process Settings:

3) To eliminate the I/O Pins only partially specified warning, launch the pin planner and set the current strength on the output pins, (I have been unable to assign the pins all to a minimum current, or all to the maximum and eliminate the warning, at least one needs to be a different value from the others, any suggestions?)

4) The minimum Verilog code simply sets the output to the input on the rising edge of a clock:

5) Delete the ADC_CLK_10 and MAX10_CLK2_50 clocks (not used in the code) to eliminate the inputs drive no logic warnings. (I closed the project and commented them out in the *.sdc and the *.qsf files, you can also delete them through the Pin Planner by clicking right on the pin name, edit and delete)
6) The resulting builds with two warnings. Which are
>> Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
and
>> Warning (169177): 11 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing MAX 10 Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.

I haven't been able to get rid of the LogicLock warning, it seems the Lite Edition seems to sets options which causes the warning in the .qsf file??

The second warning (is normal) always occurs??

Don't like to turn off warnings, but would like a clean (no warning) synthesis.


Joel
Attached Images
↧

Modelsim input signal does not coincide stimulus

January 22, 2017, 2:15 am
$
0
0
Hi all,

I made schematic type file based on LPM_Counters in Quartus 16.0 and try to simulate using Modelsim. I made stimulus to inputs in Modelsim. The problem is that input signal does not coincide stimulus (see screenshoot). I marked green arrow which wave works correctly (imput coincide stimulus). I marked white arrows where I have a problem. For example I put clock signal as stimulus (stop_clk), but input signal goes to high level and does not coincide to the clock signal.

Thank you,
Tomas

Attached Images
↧

strange timing paths in PCIe Gen3x8 AVMM DMA - Arria 10

January 22, 2017, 10:36 am
$
0
0
The design is modified starting from http://www.alterawiki.com/wiki/Refer...DMA_-_Arria_10

The path below is completely within Altera RTL, which was not modified at all, and does not even have any logic.

It looks like this is because of clock setup or timing constraints.

Any help would be greatly appreciated.

Code:
Path #1: Setup slack is -6.604 (VIOLATED)
===============================================================================
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Path Summary                                                                                                                                                                                                                                 
+--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Property          ; Value                                                                                                                                                                                                                   
+--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; From Node          ;  top:top|top_altera_pcie_a10_hip_160_6pu3ita:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|wys~ch3_pcs_chnl_hip_clk_out[0].reg                                                                       
; To Node            ;  top:top|top_altera_pcie_a10_hip_160_6pu3ita:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_
; Launch Clock      ; top|pcie_a10_hip_0|tx_clkout                                                                                                                                                                                           
; Latch Clock        ;  top:top|top_altera_pcie_a10_hip_160_6pu3ita:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|top_altera_xcvr_
; Data Arrival Time  ; 83.118                                                                                                                                                                                                                 
; Data Required Time ; 76.514                                                                                                                                                                                                                 
; Slack              ; -6.604 (VIOLATED)                                                                                                                                                                                                       
+--------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

+---------------------------------------------------------------------------------------+
; Statistics                                                                            ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
; Property                  ; Value  ; Count ; Total Delay ; % of Total ; Min  ; Max  ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
; Setup Relationship        ; 0.200  ;      ;            ;            ;      ;      ;
; Clock Skew                ; -3.347 ;      ;            ;            ;      ;      ;
; Data Delay                ; 2.640  ;      ;            ;            ;      ;      ;
; Number of Logic Levels    ;        ; 0    ;            ;            ;      ;      ;
; Physical Delays          ;        ;      ;            ;            ;      ;      ;
;  Arrival Path            ;        ;      ;            ;            ;      ;      ;
;  Clock                  ;        ;      ;            ;            ;      ;      ;
;    Clock Network (Lumped) ;        ; 1    ; 3.678      ; 100        ; 3.678 ; 3.678 ;
;  Data                    ;        ;      ;            ;            ;      ;      ;
;    IC                    ;        ; 1    ; 0.000      ; 0          ; 0.000 ; 0.000 ;
;    Cell                  ;        ; 1    ; 0.000      ; 0          ; 0.000 ; 0.000 ;
;    uTco                  ;        ; 1    ; 2.640      ; 100        ; 2.640 ; 2.640 ;
;  Required Path            ;        ;      ;            ;            ;      ;      ;
;  Clock                  ;        ;      ;            ;            ;      ;      ;
;    Clock Network (Lumped) ;        ; 1    ; 0.331      ; 100        ; 0.331 ; 0.331 ;
+---------------------------+--------+-------+-------------+------------+-------+-------+
Note: Negative delays are omitted from totals when calculating percentages

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Data Arrival Path                                                                                                                                                                                                                           
+----------+---------+----+------+--------+-------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------
; Total    ; Incr    ; RF ; Type ; Fanout ; Location                      ; HS/LP ; Element                                                                                                                                                   
+----------+---------+----+------+--------+-------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------
; 76.800  ; 76.800  ;    ;      ;        ;                                ;      ; launch edge time                                                                                                                                         
; 80.478  ; 3.678  ;    ;      ;        ;                                ;      ; clock path                                                                                                                                               
;  80.478 ;  3.678 ; R  ;      ;        ;                                ;      ; clock network delay                                                                                                                                       
;  80.478 ;  0.000 ;    ;      ; 216    ; HSSIGEN3X8PCIEHIP_L0          ;      ;  top:top|top_altera_pcie_a10_hip_160_6pu3ita:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|wys~ch3_pcs_chnl_hip_clk_out[0].reg           
; 83.118  ; 2.640  ;    ;      ;        ;                                ;      ; data path                                                                                                                                                 
;  83.118 ;  2.640 ; RR ; uTco ; 1      ; HSSIGEN3X8PCIEHIP_L0          ;      ; top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|wys|rate7[1]                                                                                                   
;  83.118 ;  0.000 ; RR ; IC  ; 3      ;  HSSICOMMONPLDPCSINTERFACE_1D5 ;      ;  top|pcie_a10_hip_0|altpcie_a10_hip_pipen1b|g_xcvr.altpcie_a10_hip_pllnphy|g_xcvr.g_phy_g3x8.phy_g3x8|phy_g3x8|g_xcvr_native_insts[7].twentynm_xcvr_native
;  83.118 ;  0.000 ; RR ; CELL ; 0      ; HSSI8GTXPCS_1D5                ;      ;  top:top|top_altera_pcie_a10_hip_160_6pu3ita:pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip
+----------+---------+----+------+--------+-------------------------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------
↧
Viewing all 19390 articles
Browse latest View live
Search
<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>