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MAX 10 interface to DDR

March 5, 2017, 1:44 am
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There a few things unclear to me in the External Memory Interface for MAX 10.
I want to interface a MAX10 10M16 in F256 package to a 1Gb DDR2 DRAM (MT47H128M16).
According to the UG-MAX10EMI I can use banks 5 and 6 for DDR interface in that package with one 8-bit DQ group each. So far so good.
Both banks have a total of 48 pins and the DDR needs 45 or 47 depending whether the DQSs are SE or differential. Still good.
Each bank has 9 DQ pins, a DM pin and a DQS/DQSn pair. This leaves 24 pins for the address/command and control signals that are actually 25.
This makes me think I can assign any unused DQ or the DQSn pins to address and control but haven't found that explicitly stated.

Can anyone shed some light on this?
Thanks in advance


Additionally, table 9 (ch. 3.3) lists "Unavailable I/O Pins While Implementing DDR3 or LPDDR2 External Memory Interfaces in Certain Device Packages" - not clear if they are not available as Memory interface os as additional I/O after the Mem Interface is assigned.
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C code syntax coloring in NIOS Eclipse editor

March 5, 2017, 5:39 am
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Hello,

Here below how C source code appears in Eclipse editor. 2nd screenshot - the same code in Notepad++.
Is there some option that allows highlight C/C++ syntax in Eclipse editor.
Thanks.

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Is there any example design to bring up transceivers with Arria V GX

March 5, 2017, 7:56 am
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Hello. We need to bring up a 8x transceivers with Arria V GX

We know that there is a example design for Arria 10 to be used with Transceiver toolkit.
Is there any design example for Arria 5 GX with which we can generate and IP and use it as a debug tool with Transceiver toolkit ?


What is the best practice to start debugging the transceivers ?


Thank you.
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Error (209037): JTAG Server can't access selected programming hardware

March 5, 2017, 10:22 am
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hello every one i have board DE1-SoC when i power in the board i sent it the code to board i have massage error and the process 42% (failed)
after i rebeat the to sent again 0%(failed)

Error (209037): JTAG Server can't access selected programming hardware
Error (209012): Operation failed
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125 MHz clock+data output

March 5, 2017, 4:26 pm
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I have a design with a CycloneIV that needs to talk to a GMII PHY, which expects data bytes on 8 parallel lines along with a clock signal.

I use a PLL to generate a 125 MHz clock, and would now like to route that to an output pin. The primitive approach gives warnings:

Warning (15058): PLL "ethernet_pll:ethernet_pll|altpll:altpll_component |ethernet_pll_altpll:auto_generated|pll1" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[0] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins
Warning (15064): PLL "ethernet_pll:ethernet_pll|altpll:altpll_component |ethernet_pll_altpll:auto_generated|pll1" output port clk[0] feeds output pin "eth_tx_clk~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance

The second warning is obvious -- I'm trying to get a clock to an output pin, which is a bad idea, that's what CLKOUT pins are for. However, if I set the pin mode, then I lose synchronization in the VHDL model between the output pin and the data bus, because now the fitter is unaware that these should be synchronized.

It appears that there is also no phase compensation mode for this case either -- I can make the PLL synchronize either the output pin or the internal clock distribution to the input clock, but if I understood correctly, I'd need both in order to get predictable behavior.

So, how do I generate both a clock and a parallel data bus at the same time?
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with MAX10 ADC connection

March 5, 2017, 11:18 pm
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Recently I am desidning a PCB and use the chip of MAX10.The detailed specific model number is 10M16SAU169I7.According to the data MAN,I connect 8 pins in BANK_1A to GND directly.Then a shotrcut occurred in my PCB.What's wrong with my design and whether I should connect the pins this way?Thanks for your time and precious answer.
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Connect split bus in verilog to output

March 6, 2017, 12:17 am
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Hello,

I believe this is a really easy question, but I have searched how to do it for a long time and I still can't figure it out. I am just now switching from VHDL to verilog.

I want to connect parts of the module to an output(the problem is with data_out):

Code:
module Tau2_LVDS(
rx_inclock,
rx_in,
rx_outclock,
data_out,
sync_frame_start,
sync_line_valid,
sync_data_invalid
);

input rx_inclock;
input [2:0] rx_in;
output rx_outclock;
output [13:0] data_out;
output sync_frame_start;
output sync_line_valid;
output sync_data_invalid;

wire rx_inclock;
wire [2:0] rx_in;
wire rx_outclock;
wire [13:0] data_out;
wire sync_frame_start;
wire sync_line_valid;
 sync_data_invalid;

wire [20:0] rx_out_wire;

wire [6:0] sync_decode_signal;

    assign rx_out_wire[20:7]=data_out[13:0];

  tau2_sync_decode sync_decoder_inst(
    .sync_in(rx_out_wire[6:0]),
    .sync_frame_start(sync_frame_start),
    .sync_line_valid(sync_line_valid),
    .sync_data_invalid(sync_data_invalid)
);
   
    tau2_lvds_deser tau2_lvds_deser_inst(
    .rx_in(rx_in),
    .rx_inclock(rx_inclock),
    .rx_out(rx_out_wire),   
    .rx_outclock(rx_outclock)
    );
endmodule
However, when I view the circuit in the RTL viewer, rx_out and data_out are not connected.

In VHDL the code used for this would look like this:
Code:
PORT MAP(rx_inclock => rx_inclock,
        rx_in => rx_in,
        rx_outclock => rx_outclock,
        rx_out(20 DOWNTO 7) => data_out(13 DOWNTO 0),
        rx_out(6 DOWNTO 0) => sync_decode_signal(6 DOWNTO 0),
);
I just can't figure out either how the verilog connections are constructed, it is quite confusing. In VHDL, when you connect something to the module in/output with =>, it is connected, end of story. Here the roles of the module ports are defined outside of the module definition, but still somehow automatically connected, and then these are somehow also automatically connected to the wires with the wires of the same name, or so it seems, except this output I try to connect. Could someone help me with this? :)
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HPS to FPGA Signal Register Issue

March 6, 2017, 2:31 am
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Using the Cyclone V SoC chipset I am currently having an issue with regards to seeing a HPS LOAN IO input coming back to the fabric of the FPGA.
I am having difficulties reading the signal in a register from a custom SPI Core I have built.

The simulation is working and it is attached to the correct LOAN IO and pin is set to an input in the VHDL code; so everything is set correctly.

I am trying to use the system console to read from a memory register that is capturing an input from the HPS LOAN IO.
Even though the signal is present on the scope HPS side no signals are being sampled into the register.

Could you advise?

Kyle
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Long FIR Filter

March 6, 2017, 3:06 am
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Hallo

I am using MATLAB and Simulink to create my model and the using the HDL coder to generate HDL code for Altera FPGA. We have a custom hardware made from ep4ce22f17c6n with I2S interface and other necessary stuffs.

We need to implement a FIR filter with around 8192 coefficients for one of our filtering requirements. But as i mentioned i am currently using MATLAB and Simulink, Simulink does not support generation of filters with more than 1024 coefficients. I also tried a way to make the filter in MATLAB in different approaches but ends up using too much resources.

I found out about the ALTERA FIR compiler, and it can make FIR filters up-to 2046 coefficients. Would it be possible to cascade several (7-8) filters of 1024 coefficients.

The final question is it actually possible to build a such a long FIR Filter in FPGA, we dont need much of the other resources from the FPGA, filtering would be the biggest task in this project.

If i am in the wrong thread, please suggest me the correct thread to post this question. Thanks in advance
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Fabric speed

March 6, 2017, 3:31 am
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Altera FPGA data sheets talk about fabric speed grades but they don't give actual fabric speeds in MHz. Can anybody tell me what the fabric speed difference between 10CX085 and 5CEFA423C7 is? Many thanks.
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Synchronizer chains not recognized

March 6, 2017, 6:32 am
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In my MAX10 project no synchronizer chains are recognized. As far as I understand a synchronizer chain begins with a asynchronous path to a register with is either:
  • a signal from a process that is clocked by an unrelated clock (different clock group) or
  • a toplevel signal that has not been associated with a clock by means of set_input_delay or set_output_delay


My single-bit sinchronizer looks as follows:

Code:
-- altera vhdl_input_version vhdl_2008

library ieee;
    use ieee.std_logic_1164.all;
   
entity bit_synchronizer is
    port(
        clk      : in    std_logic;            -- clock
        async_i  : in    std_logic;            -- async. input signal
        sync_o  : out std_logic            -- synchronized output signal
    );
end entity bit_synchronizer;

architecture rtl of bit_synchronizer is
    signal meta    : std_logic;
    signal sync : std_logic;
   
    attribute syn_preserve : boolean;
    attribute syn_keep: boolean;
    attribute syn_replicate : boolean;
    attribute syn_maxfan : integer;
   
    attribute syn_keep of meta : signal is true;
    attribute syn_keep of sync : signal is true;
    attribute syn_replicate of sync : signal is false;
    attribute syn_replicate of meta : signal is false;
    attribute syn_maxfan of meta : signal is 1;
   
    attribute altera_attribute    : string;
    attribute altera_attribute of meta : signal is "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS";
    attribute altera_attribute of rtl : architecture is "-name SDC_STATEMENT ""set_false_path -to [get_registers {*|bit_synchronizer:*|meta}]""";
begin
    process(clk)
    begin
        if(rising_edge(clk)) then
            meta <= async_i;
            sync <= meta;
        end if;
    end process;
   
    sync_o <= sync;
end architecture rtl;
I try to embed both the SDC constraints and assignments in the VHDL code to ease reuse. However, even when explicitly putting the same commands into the SDC and QSF file the synchronizer chain is not recognized. Neither the assignments nor constraints are listed as ignored in the reports.

Any ideas?
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Qsys component assignments

March 6, 2017, 8:12 am
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I've sucesfully created a custom Qsys component composed of a bunch of VHDL files and a SDC file for timing constraints. Now I would like to also add a number of assignments (set_instance_assignment -name XXX ... ) to the component. I've already tried to add a qsf file to the custom component's file list but the assignments don't seem to be applied, altough the qsf file is copied to the synthesis directory together with the VHDL and SDC files. Is that possible, or should I embedd the assignments inside the VHDL via attributes?
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Enable Pull Up resistor

March 6, 2017, 8:36 am
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Hi everyone,

I am using MAX 10 FPGA (10M02SCU169C8G) for a project and I require some of the I/Os to have a weak pull up resistor. In order to set the weak pull up resistor, the process that I have been following is as follows:

Assignments-> Assignment Editor
In the "To" column I enter the Net Name (for e.g. CONTROLLER_ENABLE_OUTPUT). Then in the "Value" column I select the parameter "Weak Pull-Up Resistor" from the drop down list. After that I select the "YES" option from the drop down in the "Enable" column.

But even then it turns out that sometimes the pull-ups are not enabled in the pin after following the above mentioned process. On doing further research I discovered a setting that I haven't been using till now. The so mentioned setting is located at:
Assignments-> Settings -> Compiler Settings -> Advanced Settings (Fitter) ->Weak Pull-Up Resistor option

The above option was found out to be Off as per the default setting. Should I enable this setting for the pull up to work.

Also Is there any other way to enable the pull up resistor using Pin Planner or by applying some constraints in the code? And is the process that I follow the correct procedure to enable pull up? I am using Quartus Prime Ver. 16.0.2.

Tanks in advance.
Regards,
Deepak
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Problems logging into myAltera

March 6, 2017, 9:09 am
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Hi,

I seem to have problems with my account:


  • login fails, as if my password was wrong
  • resetting password fails, "Unable to process your request. Please try again."
  • retrieving my user name fails, "Unable to process your request. Please try again."
  • creating a new account fails, "Our records show that you already have an [sic] myAltera account"


I've tried emailing the webmaster, but got no reply.

Does anyone else have similar problems? Is there a contact at Altera who can resolve that?

Simon
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CIC Megacore Function

March 3, 2017, 12:02 pm
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Hello everyone. I'm currently in my engineering thesis trying to implement in a FPGA a CIC Interpolation Filter. I've recentrly finished the design in fixed point using DSP Builder and i want to test my design and compare it with the CIC Megacore Function Block.

This is what the documentation say:

I read the documentation and tried to figure out how to connect the inputs of the CIC Megacore Function Block for a simple output. This is what i implemented:



But this is what i get:



The input signal is a sin wave but i only get square signal as output of the filter.

I have MATLAB R2015a and DSP Builder 16.0.1.218 running on Windows 7 64bit.
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Spice model for Power SoC?

March 6, 2017, 11:00 am
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Are there any available spice .subckt models (transient or average) for Enpirion power converters?
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Omni-Path IP

March 6, 2017, 11:12 am
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Is hard or soft IP available yet for Intel Omni-Path fabric end point?
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MPI + OpenCL Altera

March 6, 2017, 2:53 pm
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Hi everybody,

I am a master's student, I study at University of São Paulo (USP) - Brazil. Here we have an Stratix V development kit from Bittware (model s5phq_a7). I'm using OpenCL for a research project, project is a co-design of a legacy software. The board with a custom platform, so I don't to create one and all the communication is done through PCIe. The software uses MPI, which has causing me trouble with Altera OpenCL.

OpenCL demands to create five structures for properly working (Context, program, device, kernel and Queue). If I have only one process doing all the job, I have no problem during execution. But if I try to start more than one process a serious problem happens, the entire system freezes because the two (or more) process are trying to send AOCX to the same board (I have only one board, and I need to use more than one process per board). I already tried to create program structure only once (only the master creating it), and the slaves to use it, but when I do it, the slaves get segmentation fault because program structure was not created.

This happens when I set program structure, this structure is responsible to reconfigure the board through AOCX file. I would like to know if it's possible to create this structure only once and use for all process, or if OpenCL Altera allows me query the hardware reconfigured on the board and get a pointer to it. I know MPI does not allow to share variables or structures between processes. So share program structure is impossible.

Bellow It's part of my source code to show how I'm declaring theses structures:

bool init_opencl(int *n, boll *success){
cl_int status;
int ARRAY_SIZE = *n;
int nnz = ((ARRAY_SIZE*(ARRAY_SIZE-1)-1)/2);
*success = false;

if(!setCwdToExeDir()) {
*success = false;
return false;
}

platform = findPlatform("Intel(R) FPGA SDK for OpenCL(TM)");
if(platform == NULL) {
printf("ERROR: Unable to find Intel(R) FPGA OpenCL platform.\n");
*success = false;
return false;
}


device.reset(getDevices(platform, CL_DEVICE_TYPE_ALL, &num_devices));

context = clCreateContext(NULL, num_devices, device, &oclContextCallback, NULL, &status);
checkError(status, "Failed to create context");

std::string binary_file = getBoardBinaryFile(PROGRAM_FILE, device[0]);
if(*id_process == 0){ // I tried to make only master to create the program structure
program = createProgramFromBinary(context, binary_file.c_str(), device, num_devices);
}
status = clBuildProgram(program, 0, NULL, "", NULL, NULL);
checkError(status, "Failed to build program");

kernel.reset(1);
kernel[0] = clCreateKernel(program, KERNEL_FUNC, &status);
checkError(status, "Failed to create kernel");

...
}




I hope I had been clear about my problem.:)

Carlos.
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Modelsim exits with code 9

March 6, 2017, 4:43 pm
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Hi

I have been try top simulate my design using modelsim. I get no warnings when the simulation starts but after a while I see the following in my terminal:

Fatal: (vsim-4) ****** Memory allocation failure. *****
Attempting to allocate 131072 bytes
Please check your system for available memory and swap space.
** Fatal: vsimk is exiting with code 9.

I understand that it might be because the design is pretty big. But is there a way to circumvent this and simulate my design? How do I proceed? :(:( I really need the simulation to complete my project.

Kindly respond


Thanks
sudheera
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UDP socket creation on Double Exclusive Thread OS

March 6, 2017, 7:11 pm
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Hi,

Could you please suggest me how to develop a UDP / TCP socket on Double Exclusive Thread OS (Custom RTOS) using NIOS 1.1 SDK??
Are UDP or TCP socket protocol based APIs supported in NIOS 1.1 SDK?
Please do the needful...:)

Regards,
Pooja B
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