I need help . I have assignment !!
Write vhdl code for 4 bit bidirectional universal shift register using behavioral style of modeling.
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Write vhdl code for 4 bit bidirectional universal shift register using behavioral style of modeling.
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vhdl code for 4 bit bidirectional universal shift register using behavioral style of
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SLAM on FPGA using Altera OpenCL
Hello everyone,
My final year project masters project is about evaluating the performance of a SLAM (Simultaneous localisation and mapping) algorithm on an FPGA and compare it's performance with GPUs and CPUs.
The whole algorithm has roughly 10 kernels and I spent a considerable amount of time to write the kernels on C++ so that I can map and analyse the performance "per single kernel" on the platforms in the first place (while having the rest running on host CPU). My single kernels are ready now and I can now successfully run the kernel on GPU,CPU and an FPGA (emulator so far!) with OpenCL on the servers my university has given access to me.
I have a few questions and problems that I would be extremely grateful if someone can help me with.
1) Using the emulator, I timed my kernels for the FPGA. The performance of the FPGA is really really far from the GPU and CPU and since my kernels are "NDRange" I realised that the emulator does not execute the work-items in parallel to give me the correct timings. So I thought executing it on the actual FPGA for correct timing. However I get the following error:
PLL Error: Read invalid pll setting for 0.000000 MHz. Make sure read access too acl_kernel_clk is functioning and the post-quartus-script succeeded
PLL: Invalid settings f=0 m=0 n=0 k=0 c0=0 c1=0 r=0 cp=0 div=0
acl_hal_mmd.c:766:assert failure: Failed to read PLL confighost: acl_hal_mmd.c:766: l_try_device: Assertion `0' failed.
2) My supervisor told me to change the kernels from NDrange to single-work-items (since the code is originally written for a GPU with OpenCL). Having done that (by declaring for loops in the kernel itself), I got a better timing performance on an emulator but still very far from GPU and CPU. Unlike the NDrange, Is the single work item timing I am getting right via the emulator? What is the best way to avoid hours of kernel compilation time while getting a reasonable timing estimate?
3) I am interested in knowing what myNDrange performance will be on an actual FPGA and how it differs from my single work item results. Is changing the kernel from NDrange to single-work-item the right approach? if not what are your suggestions? Am I going to expect a better timing performance on an FPGA compared to GPU and CPU if I apply the optimisation methods in the guides provided?
Thanks for your help in advance.
My final year project masters project is about evaluating the performance of a SLAM (Simultaneous localisation and mapping) algorithm on an FPGA and compare it's performance with GPUs and CPUs.
The whole algorithm has roughly 10 kernels and I spent a considerable amount of time to write the kernels on C++ so that I can map and analyse the performance "per single kernel" on the platforms in the first place (while having the rest running on host CPU). My single kernels are ready now and I can now successfully run the kernel on GPU,CPU and an FPGA (emulator so far!) with OpenCL on the servers my university has given access to me.
- The FPGA on the server is Nallatech 385 with Stratix V D5 FPGA which is what I have compiled my kernels for.
- running aocl version on the server I get ( I know its old and have told my network administrator to upgrade it, if they don't I might have to stick with this ): aocl 15.0.0.145 (Altera SDK for OpenCL, Version 15.0.0 Build 145, Copyright (C) 2015 Altera Corporation)
- Querying platform info on my host code I get: OpenCL 1.0 Altera SDK for OpenCL, Version 15.0
I have a few questions and problems that I would be extremely grateful if someone can help me with.
1) Using the emulator, I timed my kernels for the FPGA. The performance of the FPGA is really really far from the GPU and CPU and since my kernels are "NDRange" I realised that the emulator does not execute the work-items in parallel to give me the correct timings. So I thought executing it on the actual FPGA for correct timing. However I get the following error:
PLL Error: Read invalid pll setting for 0.000000 MHz. Make sure read access too acl_kernel_clk is functioning and the post-quartus-script succeeded
PLL: Invalid settings f=0 m=0 n=0 k=0 c0=0 c1=0 r=0 cp=0 div=0
acl_hal_mmd.c:766:assert failure: Failed to read PLL confighost: acl_hal_mmd.c:766: l_try_device: Assertion `0' failed.
2) My supervisor told me to change the kernels from NDrange to single-work-items (since the code is originally written for a GPU with OpenCL). Having done that (by declaring for loops in the kernel itself), I got a better timing performance on an emulator but still very far from GPU and CPU. Unlike the NDrange, Is the single work item timing I am getting right via the emulator? What is the best way to avoid hours of kernel compilation time while getting a reasonable timing estimate?
3) I am interested in knowing what myNDrange performance will be on an actual FPGA and how it differs from my single work item results. Is changing the kernel from NDrange to single-work-item the right approach? if not what are your suggestions? Am I going to expect a better timing performance on an FPGA compared to GPU and CPU if I apply the optimisation methods in the guides provided?
Thanks for your help in advance.
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Nios II + DMA + OV7670 Camera
Hi everyone, I'm having problems interfacing OV7670 Data to Nios II.
The OV7670 Camera, sends pixel data from a PIO D[7:0], and this data is synchronizated with a clock called PCLK, the PCLK can be configured and the Fmax = 24 MHz to get 30 fps and the frame is configured as a 640x480 resolution, each pixel is sending in 2 bytes, now I want to performace the operation of reading the data by using DMA to store each frame into the SDRAM (Nios II is configured with SDRAM as main memory) but i don't know if is possible to synchronyzate the DMA with the PCLK clock, is it possible?
Or there is another method to read the data without get it using Nios II?
Thanks in advance!
The OV7670 Camera, sends pixel data from a PIO D[7:0], and this data is synchronizated with a clock called PCLK, the PCLK can be configured and the Fmax = 24 MHz to get 30 fps and the frame is configured as a 640x480 resolution, each pixel is sending in 2 bytes, now I want to performace the operation of reading the data by using DMA to store each frame into the SDRAM (Nios II is configured with SDRAM as main memory) but i don't know if is possible to synchronyzate the DMA with the PCLK clock, is it possible?
Or there is another method to read the data without get it using Nios II?
Thanks in advance!
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How to sned more than 32bits of data to HPS form FPGA custom ip
down votefavorite |
I am trying to access data from HPS via Avalon memory mapping interface. I have put together system in Qsys and assigned base address. In below code the I got the count value in 1st 32 bit std_logic_vector data to the HPS. But I didn't get the data in second 32 bit std_logic_vector |
use ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity en is
GENERIC(
max_pulse : INTEGER := 800; --pulses per revolution
res_bits : INTEGER := 16); --max count 2^res_bits
port(
--avlon slave inputsa and outputs
clk : in std_logic;
reset : in std_logic;
avs_s0_address : IN STD_LOGIC;
avs_s0_read : IN STD_LOGIC;
avs_s0_write : IN STD_LOGIC;
avs_s0_readdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
avs_s0_writedata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
end en;
architecture behavior of encorder is
----- avlon read
PROCESS(avs_s0_read)
BEGIN
IF avs_s0_read = '1' THEN
CASE(avs_s0_address) IS
WHEN '0' => avs_s0_readdata <= x"0f0ff0f0";
WHEN '1' => avs_s0_readdata <= x"0f0fffff";
WHEN others => avs_s0_readdata <= x"00000000";
END CASE;
ELSE avs_s0_readdata <= x"00000000";
END IF;
END PROCESS;
The way I access data from the HPS is as below,
#define COUNT 0xFF200020 //Avalon base Addrs +counter base Addrsint
main(void){
volatile int * Count_ptr = (int *) COUNT;
unsigned int cnt, ex;
while(1) {
cnt = *(Count_ptr);
ex = *(Count_ptr+1);
printf("count = %d \n",cnt);
printf("count = %d \n",ex );
}
}
0down votefavorite |
I am trying to access data from HPS via Avalon memory mapping interface. I have put together system in Qsys and assigned base address. In below code the I got the count value in 1st 32 bit std_logic_vector (count) data to the HPS. But I didn't get the data in second 32 bit std_logic_vector (count_n) |
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Why is Hardware Multiplier removed in the Gen2 nios?
I've just got chance to work with NIOSII/QSYS after a long time.
In the classic NIOSII, there are 3 flavors. I was able to use hardware multiplier in the free NIOS core.
Now in the new generation, the free economy flavor doesn't support hardware multiplication anymore. How annoying.
What makes Altera remove the hardware multiplier support? or I'm missing something?
Jeff
In the classic NIOSII, there are 3 flavors. I was able to use hardware multiplier in the free NIOS core.
Now in the new generation, the free economy flavor doesn't support hardware multiplication anymore. How annoying.
What makes Altera remove the hardware multiplier support? or I'm missing something?
Jeff
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Using PLL in the DE NANO Board
Hallo
I have a DE0-NANO board and i found out from the specification that the board has a 50 MHz clock and the FPGA in the board can support upto 200 MHz of input clock. I also understood that to change the board clock frequency i need to use one of the on board PLL.
I am developing my design in MATLAB and Simulink and then using the HDL coder to generate VHDL project, with all the necessary files. Then i put this project file in Quatras II software and want to download in the DE NANO board using the USB blaster. I am using a basic SDC file for timing constrains, and i need my design to run at 30 MHz for now. PLL comes from the ALTERA Mega core function library, my question is how can i add a pll to my design if i follow this steps?
The other idea could be to do the whole process from MATLAB HDL coder, but the DE NANO board is not supported by my version of MATLAB, so i have to create a custom board then try to work on from there.
I have a DE0-NANO board and i found out from the specification that the board has a 50 MHz clock and the FPGA in the board can support upto 200 MHz of input clock. I also understood that to change the board clock frequency i need to use one of the on board PLL.
I am developing my design in MATLAB and Simulink and then using the HDL coder to generate VHDL project, with all the necessary files. Then i put this project file in Quatras II software and want to download in the DE NANO board using the USB blaster. I am using a basic SDC file for timing constrains, and i need my design to run at 30 MHz for now. PLL comes from the ALTERA Mega core function library, my question is how can i add a pll to my design if i follow this steps?
The other idea could be to do the whole process from MATLAB HDL coder, but the DE NANO board is not supported by my version of MATLAB, so i have to create a custom board then try to work on from there.
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DE0-NANO Multiple boot files in EEPROM
Hallo
I have a DE0-NANO board from altera where i am implementing the test version of my project. There is a EEPROM in the board where we can load the boot files in sof format so every time the FPGA boots up it gets the same program, is it possible to have seperate boot files in one EEPROM or different EEPROM and the chose on based on the configuration which file should boot the FPGA, and if we change the configuration the boot file to FPGA should also change real time.
I have a DE0-NANO board from altera where i am implementing the test version of my project. There is a EEPROM in the board where we can load the boot files in sof format so every time the FPGA boots up it gets the same program, is it possible to have seperate boot files in one EEPROM or different EEPROM and the chose on based on the configuration which file should boot the FPGA, and if we change the configuration the boot file to FPGA should also change real time.
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Hardware In The Loop
Hi there,
i have a model in HIL way. it is very simple,in this model data will be multiply by a constant number then the results will be stored in a shared memory. after i run the model and compile it in quartus and program it in fpga,i should write/read data via Matlab API functions.
i read some pdf files about this but i cant figure out how to deal with this problem.
can anyone help me with this,
thanks
babak
i have a model in HIL way. it is very simple,in this model data will be multiply by a constant number then the results will be stored in a shared memory. after i run the model and compile it in quartus and program it in fpga,i should write/read data via Matlab API functions.
i read some pdf files about this but i cant figure out how to deal with this problem.
can anyone help me with this,
thanks
babak
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Where setup compiler mode (e.g. -std=C99 or -std=C11)
Hello,
Where is location in Eclipse NIOS II settings, where compiler mode can be set.
For example I want to change for more advanced mode (C99 or C11) in order to allow internal loop variable declaration, e.g.
instead of
Thanks in advance.
Where is location in Eclipse NIOS II settings, where compiler mode can be set.
For example I want to change for more advanced mode (C99 or C11) in order to allow internal loop variable declaration, e.g.
Code:
for (int i = 0; i < 10; i++)
{}Code:
int i;
for (i = 0; i < 10; i++)
{}↧
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Enabling LW H2F bridge from MPL --> hangs
Hi,
I need to enable the LW H2F bridge from HPS in order to access my FPGA logic before loading u-boot.
The MPL runs from the FPGA.
Actually, I managed to make it work, but I don't know why it works :shock:. Please see the code below. This code will hang on the first attempt to access the LW bridge, BUT if I add:
right after remapping, then the MPL runs fine. I fount this out just by coincident.
...
...
}
Thanks in advance!
I need to enable the LW H2F bridge from HPS in order to access my FPGA logic before loading u-boot.
The MPL runs from the FPGA.
Actually, I managed to make it work, but I don't know why it works :shock:. Please see the code below. This code will hang on the first attempt to access the LW bridge, BUT if I add:
Code:
ALT_PRINTF("RSTMGR %08x\n", alt_read_word(SOCFPGA_RSTMGR_ADDRESS));Code:
board_init()
{
...
...
sysmgr_pinmux_init();
releasing_all_peripherals_from_reset(); <--- added by me
warm_reset_handshake_support(); <--- added by me
alt_bridge_init(ALT_BRIDGE_LWH2F, NULL, NULL); <--- added by me
alt_write_word(ALT_L3_REMAP_ADDR, 0x18 | 0x1); // remap 0x0 to OCRAM, Maintain FPGA connection <--- moved from the end of the board_init()
// thaw (un-freeze) all IO banks
sys_mgr_frzctrl_thaw_req(FREEZE_CHANNEL_0, FREEZE_CONTROLLER_FSM_SW);
sys_mgr_frzctrl_thaw_req(FREEZE_CHANNEL_1, FREEZE_CONTROLLER_FSM_SW);
sys_mgr_frzctrl_thaw_req(FREEZE_CHANNEL_2, FREEZE_CONTROLLER_FSM_SW);
sys_mgr_frzctrl_thaw_req(FREEZE_CHANNEL_3, FREEZE_CONTROLLER_FSM_SW);...
}
Thanks in advance!
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Why only Soft PCS for Altera's XAUI IP in Arria 10 GX?
Any one know why Altera's XAUI IP for Arria 10 GX allows only soft PCS? The xcvrs have a hard 8b/10b pcs. Why is that not being used?
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Test spam issue
Hello Steve,
Here is Pavel. I hope my message will rich you.
All the best.
Pavel
Here is Pavel. I hope my message will rich you.
All the best.
Pavel
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DE0 Nano problems getting pins to work
I am working on a design with a De0 nano board, and I am having problems with getting pins to work. Quite a number of pins are working OK, but others dont output. In particular, pins A12, T13, R13, T12, do not work. I have rerouted the internal signals to other pins and they work, for instance the signal to A12 was rerouted to C9, and then works fine.
So, a couple of questions.
1/ Are all the pins on the 40 pin expansion headers dedicated to the headers, or do they have other functions?
2/ I presume all pin assignments as shown in the latest version of the user guide are correct?
3/ Is there some other way of setting up pins apart from the pin planner? Everything in there seems to be correct.
I am also having problems with Quartus, including the verbal garbage that the reports spew out. I put in two pins and although they were in the .BDF drawing, and I could partly assign pins in the pin planner, and the pin names would appear in the .BDF drawing, on compilation the compiler would not recognise these pins and gave a message that the nodes were not in the .BDF drawing!! I hand edited the .V file that the compiler generates, and got the pins to appear.
All very frustrating!
Any help gratefully received.
So, a couple of questions.
1/ Are all the pins on the 40 pin expansion headers dedicated to the headers, or do they have other functions?
2/ I presume all pin assignments as shown in the latest version of the user guide are correct?
3/ Is there some other way of setting up pins apart from the pin planner? Everything in there seems to be correct.
I am also having problems with Quartus, including the verbal garbage that the reports spew out. I put in two pins and although they were in the .BDF drawing, and I could partly assign pins in the pin planner, and the pin names would appear in the .BDF drawing, on compilation the compiler would not recognise these pins and gave a message that the nodes were not in the .BDF drawing!! I hand edited the .V file that the compiler generates, and got the pins to appear.
All very frustrating!
Any help gratefully received.
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Quartus message re output drivers
Quartus gives me a message about no output drivers on pins. I have tried putting the .alt driver on the pins, no difference. So what drivers am I supposed to put on the pins??
The quantity of useless messages output by the compiler is daunting. And half of them seem to be un-necessary. So why do it?
The quantity of useless messages output by the compiler is daunting. And half of them seem to be un-necessary. So why do it?
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Compensating for phase difference between transceiver outputs
Hi,
I'm encountering an issue concerning phase differences between transceiver output channels. Here's a description of my problem. I need to transmit eight data streams/waveforms that are generated on a Stratix IV EP4SGX230KF40C2 FPGA. The logic seems to work and the transceivers appear to be properly configured (Protocol: Basic, Subprotocol: x4, Number of Channels: 4, Block Width: 40, Base Setting: Data Rate, Effective Data Rate: 6250.0 Mbps, Input Clock Frequency: 312.5 MHz).
The problem I'm encountering is that there is a noticeable phase difference between the transceiver channel outputs. To explain, one transceiver block is associated with channels 1-4 (block one), and another transceiver block is associated with channels 5-8 (block two). If I transmit the same waveform on channels 1-4, I can confirm that they are all in phase. The same is true with channels 5-8; they are in phase. But relative to one another, channels 1-4 compared to channels 5-8, there is a noticeable phase difference.
Now I'm aware that transceiver blocks on the same side of the FPGA (right or left) can be bonded together. Specifically, I could put them in x8 bonded mode and they will be driven by the same clock network. However, I'm stuck using the Terasic TR4 development kit (http://www.terasic.com.tw/cgi-bin/pa...yNo=138&No=683) and its associated XTS-HSMC daughter cards. Unfortunately, the transceivers that I have access to are on opposite sides of the FPGA so I can't use bonded mode.
That said, is there anyway to synchronize the clocks of transceiver cores that happen to be on opposite sides of the FPGA? Any help is appreciated.
I'm encountering an issue concerning phase differences between transceiver output channels. Here's a description of my problem. I need to transmit eight data streams/waveforms that are generated on a Stratix IV EP4SGX230KF40C2 FPGA. The logic seems to work and the transceivers appear to be properly configured (Protocol: Basic, Subprotocol: x4, Number of Channels: 4, Block Width: 40, Base Setting: Data Rate, Effective Data Rate: 6250.0 Mbps, Input Clock Frequency: 312.5 MHz).
The problem I'm encountering is that there is a noticeable phase difference between the transceiver channel outputs. To explain, one transceiver block is associated with channels 1-4 (block one), and another transceiver block is associated with channels 5-8 (block two). If I transmit the same waveform on channels 1-4, I can confirm that they are all in phase. The same is true with channels 5-8; they are in phase. But relative to one another, channels 1-4 compared to channels 5-8, there is a noticeable phase difference.
Now I'm aware that transceiver blocks on the same side of the FPGA (right or left) can be bonded together. Specifically, I could put them in x8 bonded mode and they will be driven by the same clock network. However, I'm stuck using the Terasic TR4 development kit (http://www.terasic.com.tw/cgi-bin/pa...yNo=138&No=683) and its associated XTS-HSMC daughter cards. Unfortunately, the transceivers that I have access to are on opposite sides of the FPGA so I can't use bonded mode.
That said, is there anyway to synchronize the clocks of transceiver cores that happen to be on opposite sides of the FPGA? Any help is appreciated.
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Max10 E144 I/O Assignment - Need clarify re. adjacent pins and cross-coupling
Hi,
Section 3.9 of the MAX 10 General Purpose I/O User Guide states the following, re. the E144 parts:
"There is strong inductive coupling on the MAX 10 E144 lead frame package. Glitch
may occur on an input pin when an aggressor pin with strong drive strength toggles
directly adjacent to it."
My question pertains to the following pin assignments we are currently using on the Max10 prototype board, as shown in the following screen capture of the Chip Planner:
(doesn't appear I am allowed to upload images yet - image I tried to upload did not appear; following will try to describe the issue).
What the Chip Planner view shows, is a brown/tan-ish rectangle with either two, or three I/O pads. My question is, in the case where there are three pads in one of these rectangular areas, is it ok to use the upper and lower of the three, and leave the center unconnected (or driven with ~constant signal)? Or, should only one I/O pad be used in each of these rectangular regions?
Note that we are driving all signals of concern at max drive strength since timing is tight. We see a small amount of cross talk with all three of the pins in one rectangle.
Would appreciate some experienced guidance here.
Thank you.
Section 3.9 of the MAX 10 General Purpose I/O User Guide states the following, re. the E144 parts:
"There is strong inductive coupling on the MAX 10 E144 lead frame package. Glitch
may occur on an input pin when an aggressor pin with strong drive strength toggles
directly adjacent to it."
My question pertains to the following pin assignments we are currently using on the Max10 prototype board, as shown in the following screen capture of the Chip Planner:
(doesn't appear I am allowed to upload images yet - image I tried to upload did not appear; following will try to describe the issue).
What the Chip Planner view shows, is a brown/tan-ish rectangle with either two, or three I/O pads. My question is, in the case where there are three pads in one of these rectangular areas, is it ok to use the upper and lower of the three, and leave the center unconnected (or driven with ~constant signal)? Or, should only one I/O pad be used in each of these rectangular regions?
Note that we are driving all signals of concern at max drive strength since timing is tight. We see a small amount of cross talk with all three of the pins in one rectangle.
Would appreciate some experienced guidance here.
Thank you.
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Use Microchip SST25V series to configure Altera's Cyclone IV
We have earlier used M25P64 flash as configuration memory, but this family is EOL soon.
Microchip SST25V series looks both cheap and available.
For a new design based on Cyclone IV I am looking för a 16Mbit flash.
Would Microchip SST25VF016B-50-4I-S2AF work (in AS configuration mode) ?
Yes, I know the devices labeled Altera/Intel, but with the stupid Altera-pricing you don't even want to ask for "your price".
Microchip SST25V series looks both cheap and available.
For a new design based on Cyclone IV I am looking för a 16Mbit flash.
Would Microchip SST25VF016B-50-4I-S2AF work (in AS configuration mode) ?
Yes, I know the devices labeled Altera/Intel, but with the stupid Altera-pricing you don't even want to ask for "your price".
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How to time constrain output pin connected to input pin on the same FPGA (design) ?
Hello,
My design has output pin SYNC_OUT and input pin SYNC_IN, both synchronous, clocked by same clock. Pins connected externally on PCB with known max and min board delay.
How do I constrain these ports to meet timing from SYNC_OUT to SYNC_IN? I don't know any setup or hold times as both ports are on the same FPGA.
Thaks in advance
Vladimir
My design has output pin SYNC_OUT and input pin SYNC_IN, both synchronous, clocked by same clock. Pins connected externally on PCB with known max and min board delay.
How do I constrain these ports to meet timing from SYNC_OUT to SYNC_IN? I don't know any setup or hold times as both ports are on the same FPGA.
Thaks in advance
Vladimir
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MAX 10 NEEK Quartus
Hi all,
I want to monitor power on the fpga board when a video fro HDMI i/p is played on the LCD screen.
In the Design examples, there is a code for power monitor and another one for HDMI.
Any suggestions as to how should I start??
I am new to FPGA's .
I want to monitor power on the fpga board when a video fro HDMI i/p is played on the LCD screen.
In the Design examples, there is a code for power monitor and another one for HDMI.
Any suggestions as to how should I start??
I am new to FPGA's .
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Control NIOS II program from "NIOS II Console" (without HAL functions)
Hello,
I'm trying to implement control of NIOS II program from NIOS II Console.
Here is snippet of code:
The sw_get_command is called from while(1) loop.
If button 2 is pressed (condition btn & 0x04), user is invited to type some value in NIOS II Console.
The value can have multiple symbols.
I'm faced to problem how to read all symbols. Actually when I read a symbol (in the command data_reg = IORD(JTAG_UART_BASE, JUART_DATA_REG_OFT)), it seems that read FIFO is erased.
Otherwise how to explain that after leaving the do-while loop, the value of ravail (number of characters remaining in the read FIFO) is 0 (1st image - screenshot of NIOS II console).
Another question: after some "exercises" with button 2, the communication crashes and Eclipse becomes unavailable (2nd screenshot - fragment of Windows Task Manager screenshot).
Thanks in advance.
![]()
I'm trying to implement control of NIOS II program from NIOS II Console.
Here is snippet of code:
Code:
void sw_get_command(cmd_type *cmd) {
alt_u8 btn;
btn = (alt_u8) btn_read(BTN_BASE) & 0xf; // read 4 pushbuttons
if (btn != 0) { // a button pressed
if (btn & 0x01) // button 0 pressed
cmd->pause = cmd->pause ^ 1; // toggle pause bit
if (btn & 0x02) // button 1 pressed
cmd->prd = pio_read(SWITCH_BASE) & 0x03ff; // load new interval
if (btn & 0x04)
{
alt_u8 rvalid = 0;
alt_u32 data_reg = 0;
do{
data_reg = IORD(JTAG_UART_BASE, JUART_DATA_REG_OFT);
rvalid = data_reg >> 15 & 0x01;
} while (rvalid == 0);
printf("data = %c\n", (char)data_reg & 0xff);
printf("ravail = %d\n", (data_reg >> 16) & 0xffff);
}
btn_clear(BTN_BASE);
}
}If button 2 is pressed (condition btn & 0x04), user is invited to type some value in NIOS II Console.
The value can have multiple symbols.
I'm faced to problem how to read all symbols. Actually when I read a symbol (in the command data_reg = IORD(JTAG_UART_BASE, JUART_DATA_REG_OFT)), it seems that read FIFO is erased.
Otherwise how to explain that after leaving the do-while loop, the value of ravail (number of characters remaining in the read FIFO) is 0 (1st image - screenshot of NIOS II console).
Another question: after some "exercises" with button 2, the communication crashes and Eclipse becomes unavailable (2nd screenshot - fragment of Windows Task Manager screenshot).
Thanks in advance.
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