Documentation is confusing about calls and synchronization

May 4, 2017, 2:44 am

≪ Previous: Does Seriallite III for Arria10 have programmable pre-emphasis & equalizer settings?

Hello,
I am reading the OpenCL documentation, and I found two major confusing concepts:

1. It is mentionned in page 28 of the Programming Guide that: "for a given kernel, you can only assign one call site per channel ID" (the same for pipes), and then they used many times multiple calls to the same channel and in the same kernel, and even used in loops (page 31 and 33).
Can anyone clarify this detail to me?

2. In the synchronization of pipes (example page 56), why when we use blocking attribute the calls are not ordered, and we need to add fences (mem_fence()), how can the calls be blocking and not ordered in the same time ?

↧

altera_dma driver for PCIe

May 4, 2017, 6:01 am

≫ Next: VIdeo Color Space Converter IP core

≪ Previous: Documentation is confusing about calls and synchronization

Hi everyone, i'm using an Arria V starter kit for PCIe application and i used the reference design posted in altera wiki. The application software reported success in one PC but not in other with different features. The driver code is installed in two with success but in one, user application reported timeout for read, write and simultaneous RW. Had anyone has the same problem? Have anyone some suggestion about what can i do to try solve this problem?

↧

VIdeo Color Space Converter IP core

May 4, 2017, 8:03 am

≫ Next: Continuous signal tap capture?

≪ Previous: altera_dma driver for PCIe

Hi,

I plan to use Clocked Video Input II + Color Space Converter II + Clocked Video Output II.
I generated these IP cores from Qsys with the associated testbenches.
I tried to simulate the design with modelsim and I noticed that data_out stream of the CVO-II is always XXXXX. Did someone simulate the CVO-II please?

Best regards,

Alexandre

↧

Continuous signal tap capture?

May 4, 2017, 8:42 am

≫ Next: Working with MAX3000 family

≪ Previous: VIdeo Color Space Converter IP core

Hi,

I am wondering if there is a way to continuously get data from probes in signal tap.

I have explored the mex matlab signal tap functionality in a loop but I lose samples.
I have briefly tried tcp/ip tcl server and signal probes functionality and I lose samples.

Are there double buffering schemes in signal tap?
Do I need to implement my own system (double buffered memory) to not lose samples?
The signal I am hoping to capture continuously is a 16 bit word updating at 56khz.

Thanks!

↧

Working with MAX3000 family

May 4, 2017, 11:18 am

≫ Next: MII TSE Deisgn

≪ Previous: Continuous signal tap capture?

Hi!

I need to program some EPM3032 CPLDs.
The bdf file was generated by Quartus version 13, free download. According the warning after compilation, this version doesn´t generate programming files like *.pof and *.jam. I've tried also Quartus 13 web version, unsuccessfully.
The question is:
What can i do to generate programming files?

Best Regards

Joel

↧

MII TSE Deisgn

May 4, 2017, 12:30 pm

≫ Next: BSP Editor - Operating System Section only display generic preloader

≪ Previous: Working with MAX3000 family

Hello,

i have a few problems with my TSE design. I want to use MII between the MAC and PHY (DP83848C), which is supported by the IP-Core.
I have successfully set up a communication over RGMII on the DE2-115 board from Terasic with the help of a guide from Altera, "Using Triple-Speed Ethernet on DE2-115 Boards". Now I want to port the system to a DE0-Nano with an external PHY.
I choose GMII/MII in the TSE configuration, I use my code from the DE2-115 board with a few changes for 100MBit mode, the LEDs on the external board are blinking, but I cant receive anything. I think there is something wrong with my PHY initialization, but I don't know what. Is someone here who has a full working setup with the DP83848C over MII? I'm working with Quartus 16.1 and don't use Iniche or something, I want to use the plain C interface like in de guideline from Altera.
If there is something more you want to know, don't be afraid to ask.

Hope for a reply,
Donni

↧

BSP Editor - Operating System Section only display generic preloader

May 4, 2017, 1:17 pm

≫ Next: Strange comparator behavior

≪ Previous: MII TSE Deisgn

Hello everyone,

I currently have Quartus II and SoC EDS (version 15.0) installed on both windows 7 and Ubuntu 16.04. I noticed when I tried to create a New BSP using the BSP editor under Linux, the Software section under Operating System only displays "Preloader", while on my windows system it shows both "U-Boot SPL Preloader Cyclone V/..." and "U-Boot Bootloader (Arria 10 HP)."

Is there a way to have both the windows options (U-Boot SPL Preloader Cyclone V/... and "U-Boot Bootloader (Arria 10 HP))appear under my linux version of BSP editor?

Thanks for taking the time to read through my question. Any help is appreciated.

↧

Strange comparator behavior

May 4, 2017, 1:25 pm

≫ Next: Quartus II will detect custom vendor ID

≪ Previous: BSP Editor - Operating System Section only display generic preloader

I have a simple comparator project which compares two 2-bit words. I wrote a code, but time diagrams show some strange behavior:

Code:

library IEEE;

use IEEE.std_logic_1164.all;

entity cmp is

port ( x0, x1, y0, y1, L, E, G : in std_logic;

Lo,Eo,Go : out std_logic);

end cmp;

architecture behav of cmp is

signal LEG: std_logic_vector(0 to 2);

begin

process (x0,x1,y0,y1,L,E,G)

begin

    if x1>y1 then LEG<="001";

    elsif x1<y1 then LEG<="100";

    else

        if x0>y0 then LEG<="001";

        elsif x0<y0 then LEG<="100";

        else 

            if G='1' then LEG<="001";

            elsif L='1' then LEG<="100";

            else LEG<="010";

            end if;

        end if;

    end if;

end process;

Lo<=LEG(0); Eo<=LEG(1); Go<=LEG(2);

end behav;

I looked through my code but didn't find a mistake which makes for example "Go" output to fall and rise near the 50th ns. Is it my mistake or maybe Max+Plus II (v.10.0) bug?

Attached Images

comparator.PNG (8.6 KB)

↧

Quartus II will detect custom vendor ID

May 4, 2017, 10:07 pm

≫ Next: Quartus Software Licence

≪ Previous: Strange comparator behavior

Hi,
I'm planning to develop a new FPGA board with altera Max 10 FPGA and on-board USB-Blaster. Whether quartus II will detect vendor ID(my own VID) of my new board. If anyone helps, it would be great.

Thanks,
Lakshmi

↧

Quartus Software Licence

May 4, 2017, 10:13 pm

≫ Next: Bank definition and voltage levels on different (Sub?)Banks

≪ Previous: Quartus II will detect custom vendor ID

When i click on the Run Timing Simulation there is one error
which shows that Unable checkout the licence files
1. MGLS_LICENSE_FILE
2. LM_LICENSE_FILE.
Should i upgrade to licensed version to complete the simulation?

↧

Bank definition and voltage levels on different (Sub?)Banks

May 5, 2017, 1:23 am

≫ Next: Not able to program EPCQ on cyclone 5e dev board

≪ Previous: Quartus Software Licence

Hi,
Can You provide some kind of clarification: when the documentation states that the banks of FPGAs can have different voltage standards does this statement refers to different bank numbers or subbanks (i dont know how to call them?).
I mean:
I know i can power BANK 3 and BANK 7 with different voltages
but,
can I power BANK7B and BANK7C with different voltages?

Does they count as different Banks?

All this (SUB?)Banks have their separate power supply and predrivers accordingly (In Cyclone V SoC for example).

↧

Not able to program EPCQ on cyclone 5e dev board

May 5, 2017, 1:45 am

≫ Next: DE0-NANO Board External Clock

≪ Previous: Bank definition and voltage levels on different (Sub?)Banks

Hi

I use the DK-DEV-5CEA7N/P dev board that use FPP configuration as default.
I am trying to change this to using AS to program the EPCQ device.

When I try to program the EPCQ with quartus flash programmer I get the following error:
Error (209025): Can't recognize silicon ID for device 1. A device's silicon ID is different from its JTAG ID. Verify that all cables are securely connected, select a different device, or check the power on the target system. Make sure the device pins are connected and configured correctly.

Here is what I have done:
Changed the two resistors from R16 to R18 and from R22 to R23.
Set SW1 that controls the MSEL bits to:
MSEL0 OFF
MSEL1 OFF
MSEL2 ON
MSEL4 OFF
MSEL3 is connected to ground.

I am using quartus prime 16.0

Is there anything else I need to do?
Have anyone else been able to program the EPCQ on this dev board?

Torstein

↧

DE0-NANO Board External Clock

May 5, 2017, 2:31 am

≫ Next: system console

≪ Previous: Not able to program EPCQ on cyclone 5e dev board

Hallo

So i have a DE0-NANO Board, and i tried to replace the on board oscillator with a external clock. I took out the on board oscillator and connected my external clock pin to pin 3 of the on board oscillator connection. I replaced the on board oscillator with a 22.5 MHz clock. Now the problem is when i try to synthesize the design i get a error at my top level clock module file. I dont use any pll and run my design with the same frequency as the external clock. I am attaching the vhdl file where it indicates and error and the error message is following

Error (10518): VHDL type mismatch error at FPGA_top_clock_module.vhd(62): integer type does not match real literal File: FPGA_top_clock_module.vhd Line: 62
so the error points to line 62 and in line 62 it states that inclk0_input_frequency => 4.428855e+04,

so does this mean that i am only getting 44.2 KHz as my input clock to the FPGA????

Attached Files

FPGA_top_clock_module.vhd (2.8 KB)

↧

system console

May 5, 2017, 10:05 am

≫ Next: Error (15462): DSP block multiplier WYSIWYG how to correct ?

≪ Previous: DE0-NANO Board External Clock

hello,

I would use the master_write_memory command of the system console tool with the -format option to avoid byte-size transfers (as documented in the Quartus Prime v16.1 Standard Edition Handbook vol3, p. 1675) but the command generates an error. It works without the -format option for a byte transfer.
The master_read_memory command works fine with the -format option. Please find below the command used:

master_write_memory -format 32 $claim_path [expr $BaseAddr + $Ctrl] 1

(BaseAddr and Ctrl variables have been previously defined with a set command).

Thank you in advance for your help.

Thierry

↧

Error (15462): DSP block multiplier WYSIWYG how to correct ?

May 5, 2017, 10:31 am

≫ Next: Problem with PCIe Root Port on the Altera Cyclone V

≪ Previous: system console

Ｉｒｕｎ　ｔｈｅ　ｆｉｔｔｅｒ　ｅｎｃｏｕｎｔｅｒ　ｆａｉｌ　ａｓ　ｂｅｌｏｗｓ　ｍｅｓｓａｇｅ：

Error (15462): DSP block multiplier WYSIWYG primitive "Stage3_Encode:s3|FIR_FilterBank:fir_fb1|FIR4:f4|a ltmult_add:Add3_rtl_0|mult_add_td44:auto_generated |mac_mult2" has its scan chain connected, but the dedicated scan chains are not used for the DSP block

ｃｏｕｌｄ　ｐｌｓ　ｈｅｌｐ　ｍｅ　ｈｏｗ　ｔｏ　ｒｅｓｏｌｖｅ　ａｂｏｕｔ　ｔｈｉｓ　ｐｒｏｂｌｅｍ？

Ｔｈａｎｋｓ！
Ｍｉｃｈａｅｌ

↧

Problem with PCIe Root Port on the Altera Cyclone V

May 5, 2017, 9:56 am

≫ Next: Synthesized away the following RAM node help

≪ Previous: Error (15462): DSP block multiplier WYSIWYG how to correct ?

Hi guys,

I have problems testing the PCIe Root Port on the Altera Cyclone V Dev Kit. Hope someone has encountered this problem before and have a solution?

I loaded the prebuilt image sd_card_image_cyclone5.bin and followed the steps from the link below, but it failed at "insmod altera_rpde.ko". Has anyone had this issue?

https://rocketboards.org/foswiki/vie...ootPortWithMSI

I am using the Altera Cyclone V Dev Kit with a Gigabit Ethernet Controller as called out by the Hardware Requirements.

Root Port: Cyclone V SoC Development Kit (5CSXFC6)
Endpoint: Intel® Gigabit CT Desktop Adapter (Intel® 82574L Gigabit Ethernet Controller)

Test Results:
root@cyclone5:/mnt# insmod altera_epde.ko
root@cyclone5:/mnt# insmod altera_rpde.ko
altera-rpde pcie_rpde.1: has no require EP detected

Of course, it failed to run ./dmaxfer:
root@cyclone5:/mnt# ./dmaxfer
EP block fail to open
Fail to get data transfer size
root@cyclone5:/mnt#

↧

Synthesized away the following RAM node help

May 5, 2017, 2:16 pm

≫ Next: Boot loader, Cyclone 3 reconfiguration, in-circuit EPCS update

≪ Previous: Problem with PCIe Root Port on the Altera Cyclone V

Hi all,

when I compile my code, I receive the warning which my RAM nodes q_a is synthesized away. (Not sure what does this mean)

I have two RAMs, m1 and m2, both 32x128 true dual port rams. What I do is the following:

1. Read 2 numbers from m1, and input q_a & q_b into a compare module and save the smaller one to m2. (Try to implement Merge Sort between 2 RAMs)
2. After all the number is compared, transfer data back to m1.

The following is the code of connecting the components (RAM1, RAM2 to compare hardware module)

Code:

... ...

MgHwM : merg_hw_module 

PORT MAP (

  ... ...

    ToM1AdrA           => m1_adr_a,

    ToM1AdrB           => m1_adr_b,

    ToM1DataA          => m1_data_a,

    ToM1DataB          => m1_data_b,

    ToM1RdenA          => m1_rden_a,

    ToM1RdenB          => m1_rden_b,

    ToM1WrenA          => m1_wren_a,

    ToM1WrenB          => m1_wren_b,

    FromM1QA           => m1_q_a, ------------------------------------------------- q_a of m1 is enter via this port

    FromM1QB           => m1_q_b, ------------------------------------------------- q_b of m1 is enter via this port

    ToM2AdrA           => m2_adr_a,

    ToM2AdrB           => m2_adr_b,

    ToM2DataA          => m2_data_a,

    ToM2DataB          => m2_data_b,

    ToM2RdenA          => m2_rden_a,

    ToM2RdenB          => m2_rden_b,

    ToM2WrenA          => m2_wren_a,

    ToM2WrenB          => m2_wren_b,

    FromM2QA           => m2_q_a, ----------------------------------------------- q_a of m2 is enter via this port

    FromM2QB           => m2_q_b ------------------------------------------------ q_b of m2 is enter via this port

);

And the following is the compare code:

Code:

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.NUMERIC_STD.ALL;





ENTITY merg_hw_module IS

    PORT (

        -- SYSTEM PORT

        mhm_clk            : IN STD_LOGIC := '0';

        mhm_SendToSortDATA : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);

        -- from merg_state_machine_module PORT

        mhm_start_en : IN STD_LOGIC;

        mhm_bound_en : IN STD_LOGIC;

        mhm_pair_ubound : IN INTEGER;

        mhm_rd1_ubound : IN INTEGER;

        mhm_rd2_ubound : IN INTEGER;

        mhm_rd2_initval : IN INTEGER;

        mhm_SendDataStart  : IN STD_LOGIC := '0';

        -- to merg_state_machine_module PORT

        mhm_bound_done : OUT STD_LOGIC;

        mhm_state_done : OUT STD_LOGIC;

        -- ports to mem1

        ToM1AdrA : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);

        ToM1AdrB : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);

        ToM1DataA : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);

        ToM1DataB : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);

        ToM1RdenA : OUT STD_LOGIC := '0';

        ToM1RdenB : OUT STD_LOGIC := '0';

        ToM1WrenA : OUT STD_LOGIC := '0';

        ToM1WrenB : OUT STD_LOGIC := '0';

        FromM1QA : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

        FromM1QB : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

        -- ports to mem2

        ToM2AdrA : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);

        ToM2AdrB : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);

        ToM2DataA : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);

        ToM2DataB : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);

        ToM2RdenA : OUT STD_LOGIC := '0';

        ToM2RdenB : OUT STD_LOGIC := '0';

        ToM2WrenA : OUT STD_LOGIC := '0';

        ToM2WrenB : OUT STD_LOGIC := '0';

        FromM2QA : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

        FromM2QB : IN STD_LOGIC_VECTOR (31 DOWNTO 0)

    );

END ENTITY;





ARCHITECTURE rt OF merg_hw_module IS





BEGIN

merg: PROCESS (mhm_clk) 

VARIABLE rd1 : INTEGER := 0;

VARIABLE rd2 : INTEGER := 0;

VARIABLE ele_num : INTEGER;

VARIABLE full_rd1 : INTEGER;

VARIABLE full_rd2 : INTEGER; 

VARIABLE wr : INTEGER := 0;

VARIABLE wr2 : INTEGER := 0;

VARIABLE pair : INTEGER := 0;

BEGIN

    IF (RISING_EDGE(mhm_clk)) THEN

        ------------------------------------------------

        -- assign the parameter value

        ------------------------------------------------

        IF (mhm_bound_en = '1') THEN

            rd1 := 0;

            rd2 := mhm_rd2_initval;

            wr  := 0;

            wr2 := 0;

            rd_delay := 0;

            pair := 0;

            mhm_bound_done <= '1';

        ELSE

            mhm_bound_done <= '0';

        END IF;

        ------------------------------------------------

        -- Mrg sort from RAM1 to RAM 2

        --

        ------------------------------------------------

        IF (mhm_start_en = '1') THEN

            IF (pair < mhm_pair_ubound) THEN

                IF (rd1 < mhm_rd1_ubound) AND (rd2 < mhm_rd2_ubound) THEN

                    full_rd1 := rd1 + ele_num * pair;

                    full_rd2 := rd2 + ele_num * pair;

                    ToM1RdenA <= '1';

                    ToM1RdenB <= '1';

                    ToM1AdrA <= STD_LOGIC_VECTOR (TO_UNSIGNED(full_rd1, 7));

                    ToM1AdrB <= STD_LOGIC_VECTOR (TO_UNSIGNED(full_rd2, 7));

                    IF (rd_delay < 3) THEN

                        rd_delay := rd_delay + 1;

                    ELSE

                        IF (FromM1QA = FromM1QB) THEN

                            ToM2WrenA <= '1';

                            ToM2AdrA <= STD_LOGIC_VECTOR (TO_UNSIGNED(wr, 7));

                            ToM2DataA <= FromM1QA;

                            rd1 := rd1 + 1;

                            wr := wr + 1;

                            rd_delay := 0;

                        ELSIF (FromM1QA < FromM1QB) THEN

                            ToM2WrenA <= '1';

                            ToM2AdrA <= STD_LOGIC_VECTOR (TO_UNSIGNED(wr, 7));

                            ToM2DataA <= FromM1QA;

                            rd1 := rd1 + 1;

                            wr := wr + 1;

                            rd_delay := 0;

                        ELSIF (FromM1QA > FromM1QB) THEN

                            ToM2WrenA <= '1';

                            ToM2AdrA <= STD_LOGIC_VECTOR (TO_UNSIGNED(wr, 7));

                            ToM2DataA <= FromM1QB;

                            rd2 := rd2 + 1;

                            wr := wr + 1;

                            rd_delay := 0;

                        END IF; -- end for if elsif

                    END IF; -- end for rd_delay

                ELSIF (rd1 < mhm_rd1_ubound) OR (rd2 < mhm_rd2_ubound) THEN

                    full_rd1 := rd1 + ele_num * pair;

                    full_rd2 := rd2 + ele_num * pair;

                    ToM1RdenA <= '1';

                    ToM1RdenB <= '1';

                    ToM1AdrA <= STD_LOGIC_VECTOR (TO_UNSIGNED(full_rd1, 7));

                    ToM1AdrB <= STD_LOGIC_VECTOR (TO_UNSIGNED(full_rd2, 7));

                    IF (rd_delay < 3) THEN

                        rd_delay := rd_delay + 1;

                    ELSE

                        IF (FromM1QA = FromM1QB) THEN

                            ToM2WrenA <= '1';

                            ToM2AdrA <= STD_LOGIC_VECTOR (TO_UNSIGNED(wr, 7));

                            ToM2DataA <= FromM1QA;

                            rd1 := rd1 + 1;

                            wr := wr + 1;

                            rd_delay := 0;

                        ELSIF (FromM1QA < FromM1QB) THEN

                            ToM2WrenA <= '1';

                            ToM2AdrA <= STD_LOGIC_VECTOR (TO_UNSIGNED(wr, 7));

                            ToM2DataA <= FromM1QB;

                            rd2 := rd2 + 1;

                            wr := wr + 1;

                            rd_delay := 0;

                        ELSIF (FromM1QA > FromM1QB) THEN

                            ToM2WrenA <= '1';

                            ToM2AdrA <= STD_LOGIC_VECTOR (TO_UNSIGNED(wr, 7));

                            ToM2DataA <= FromM1QA;

                            rd1 := rd1 + 1;

                            wr := wr + 1;

                            rd_delay := 0;

                        END IF; -- end for if elsif

                    END IF; -- end for rd_delay

                ELSE

                    pair := pair + 1;

                    rd1 := 0;

                    rd2 := mhm_rd2_initval;

                END IF;

            ELSE -- current finish the sort, send data back to m1

                IF (rd1 < 128) THEN

                    ToM2RdenB <= '1';

                    ToM2AdrB <= STD_LOGIC_VECTOR (TO_UNSIGNED(rd1, 7));

                    rd1 := rd1 + 1;

                END IF; -- end for rd1

                IF (rd_delay < 3) THEN

                    rd_delay := rd_delay + 1;

                ELSE

                    IF (wr2 < 128) THEN

                        ToM1WrenA <= '1';

                        ToM1RdenA <= '0';

                        ToM1AdrA <= STD_LOGIC_VECTOR(TO_UNSIGNED(wr2, 7));

                        ToM1DataA <= FromM2QA;

                    ELSE

                        rd_delay := 0;

                        rd1 := 0;

                        ToM1WrenA <= '0';

                        mhm_state_done <= '1';

                    END IF;

                END IF;

            END IF;

        ELSE

            mhm_state_done <= '0';

        END IF;

        ---------------------------------------------

        --         send data to srt

        --  currently, sorted data is stored at m2

        ---------------------------------------------

        IF (mhm_SendDataStart = '1') THEN

            IF (rd1 < 128) THEN

                ToM1RdenB <= '1';

                ToM1AdrB <= STD_LOGIC_VECTOR (TO_UNSIGNED(rd1, 7));

            END IF; -- end for rd1

            IF (rd_delay < 3) THEN

                rd_delay := rd_delay + 1;

            ELSE

                mhm_SendToSortData <= FromM1QB;

            END IF; -- end for rd_delay

        END IF; -- end for mc_SendToSortEn

    END IF;

END PROCESS;

END ARCHITECTURE;

For some reason, the q_a for m1 (which corresponding the FromM1QA), the q_b for m2 (which corresponding to FromM2QB ) are synthesized away.

Can anyone help?

Thanks.

↧

Boot loader, Cyclone 3 reconfiguration, in-circuit EPCS update

May 6, 2017, 2:12 am

≫ Next: [Help] Code verilog or building QYSY for adaptive noise cancellation using LMS

≪ Previous: Synthesized away the following RAM node help

I developed the device based on Cyclone 3 with its config programmed into EPCS16 using active serial mode.
To upgrade configuration external device and external software (e.g. byteblaster/usb blaster + Quartus II) are needed.
I was asked if it is possible to design in the way that EPCS image is updated "in-circuit" (by the devices located on the board).
In my design NCONFIG, CONF_DONE and NCE are going to AS config connector only, and NSTATUS goes nowhere.

I did brief research on how Cyclone configures, but still do not have answer to this question.
In my understanding it may be that EPCS is having several sections, first section with boot loader which configures FPGA providing r/w access interface to connected EPCS chip, the second section is "user configuration" (the main config used for device operation). When boot loader loads, and then can not load "user config", it keeps in boot loader mode accepting update of the EPCS device. This is needed in case user image is corrupt for some reason (e.g. bad update attempt).

Is there any way to achieve this goal, given that those control signals are not fed back to FPGA?
Or maybe I still miss something and it should be done differently?
Thank you.

↧

[Help] Code verilog or building QYSY for adaptive noise cancellation using LMS

May 6, 2017, 8:18 am

≫ Next: VIdeo Color Space Converter IP core

≪ Previous: Boot loader, Cyclone 3 reconfiguration, in-circuit EPCS update

My project required using Least Mean Square (LMS) algorithm for adaptive noise cancellation on DE2 board. Anyone here can help me ( teach me ) how to do that ? . i prefer using QYSY . Thanks all

P/s : Sorry for my bad english

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VIdeo Color Space Converter IP core

May 4, 2017, 8:03 am

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≪ Previous: [Help] Code verilog or building QYSY for adaptive noise cancellation using LMS

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