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Help with setting up Cyclone V GT dev kit

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Hi,

I just bought a Cyclone V GT dev kit from Altera, planing to write OpenCL program and evaluate it.
I'm using Window 10 Education with Intel Core i7.
I'm having some problem getting it to work, following the User's guide instruction.
I've install Quartus Prime 17.0 (include Cyclone V driver) , Cyclone V GT kit installation (version 13), USB-Blaster II

First, after I run "aocl install" it returned success for both kernel driver and board driver.
But then if I run "aocl diagnose" it will return

Unable to open the kernel mode driver.

Please make sure you have properly installed the driver. To install the driver, run
aocl install

Second, it can auto detect the board in Quartus Prime->Programmer->Auto Detect
then I tried the "Add File" and add the factory recovery .sof file and run it, it will fail without showing any message.

Third, the Board Test System from the kit installation failed to launch without any error message, nothing showed up when I double click it.
I tried Win8/Win7 compatible mode, didn't work.

Any help is appreciated.
Thanks!

HelloWorld - compiler error, not able to generate hardware

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Hello,

Recently I bought the DE1-SoC Board for trying OpenCL with it.
- I set up the environment variables like suggested in the "DE1SOC_OPENCL.pdf"
- I have a valid licence.
- I have downloaded the BSP for the Board

After trying to compile a .cl -File (the vector_add example from the intel site) with the command:
aoc device/vector_add.cl -o bin/vector_add.aocx --report --board de1soc_sharedonly

I get the error: Compiler Error, not able to generate hardware.
The .log file gave me following error-text:

...
Info (21057): Implemented 12069 device resources after synthesis - the final resource count might be different
Info (21058): Implemented 13 input pins
Info (21059): Implemented 45 output pins
Info (21060): Implemented 57 bidirectional pins
Info (21061): Implemented 10410 logic cells
Info (21064): Implemented 1528 RAM segments
Info (21065): Implemented 1 PLLs
Info (21071): Implemented 1 partitions
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 65 warnings
Info: Peak virtual memory: 1136 megabytes
Info: Processing ended: Mon May 15 07:23:33 2017
Info: Elapsed time: 00:00:32
Info: Total CPU time (on all processors): 00:00:31
Error (281039): Finished parallel synthesis of 1 partition(s). 1 partitions did not finish parallel synthesis because there were errors
Error (281040): Partition "system_acl_iface_hps_hps_io_border:border" did not complete synthesis due to errors
Info (144001): Generated suppressed messages file /home/developer/workspace/opencl_intel_tutorial/opencl_example_vector_soc/vector_add/bin/vector_add/top.map.smsg
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 2 errors, 581 warnings
Error: Peak virtual memory: 1575 megabytes
Error: Processing ended: Mon May 15 07:26:48 2017
Error: Elapsed time: 00:04:42
Error: Total CPU time (on all processors): 00:04:56
Error (293001): Quartus Prime Full Compilation was unsuccessful. 4 errors, 581 warnings
Error: Flow compile (for project /home/developer/workspace/opencl_intel_tutorial/opencl_example_vector_soc/vector_add/bin/vector_add/top) was not successful
Error: ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last.


Error (23031): Evaluation of Tcl script /home/developer/intelFPGA_lite/16.1/quartus/common/tcl/internal/qsh_flow.tcl unsuccessful
Error: Quartus Prime Shell was unsuccessful. 11 errors, 581 warnings
Error: Peak virtual memory: 806 megabytes
Error: Processing ended: Mon May 15 07:26:49 2017
Error: Elapsed time: 00:04:50
Error: Total CPU time (on all processors): 00:05:04


Google said that that "Error: Peak virtual memory: 806 megabytes" means that i´m using to much logic elements, but its just the vector-add example so I´m quite confused.
I hope someone can point out whats the problem.

Thanks :)

Cyclone V Hard memory controller rate

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Hi, I am using Cyclone V which has 2 Hard memory controllers. When I tried to generate DDR3 memory controller with Uniphy I was not able to select Half or Quarter rate on Avalon-MM interface. Then I came to know that hard memory interface supports only full-rate controller mode. I want to run local interface at lower rate(Quarter/Half) with higher data width. How to do this when I am using Hard memory controller?

on chip memory on system

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i try use sram instead of on chip memory on system and my system has 3 components such as nios, jtag uart, sram. Help me!

Sobel filter with opencl on FPGA

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I am going through the altera opencl implementation of sobel filter for FPGAs (code is shown below).
I understand that they are using line buffers, which are then implemented as shift registers on the FPGA. Now they initialize the line buffer to have 2 rows and 3 extra pixels (which is needed for a window). I understand the sliding window concept where each pixel is buffered, and when enough pixels are available, the output is produced.
In this implementation, assume a 4 x 4 image. Now 11 pixels are buffered (2 * COLS + 3). Initially count is used to initialize the buffer to zero (I don't think this is necessary because the initial array itself can be initialized to zero). Now when count is zero, the pixel at position zero is obtained ( rows[0] = count >= 0 ? frame_in[count] : 0 ), and multiplied with the corresponding kernel coefficient and place at frame_out [0]. But in the normal convolution, to calculate the value at position zero, we need the neighboring pixels, which in this case is (0,1,4,5 and border pixels). So why are they placing only one value at position zero. Am I missing something here?.
0 1 2 3
4 5 6 7
8 9 10 11
12 13 14 15
In the matrix above, to calculate the value for pixel 5, we convolve the kernel with pixels 0,1,2,4,5,6,8,9,10. The same thing happens in the code below, but the output is stored at frame_out[10] (actually should be at frame_out[5]?).
code reproduced below:
frame_in is the input image, frame_out is the output image, iterations is the image size (rows*cols) and threshold is 128.




// Copyright (C) 2013-2016 Altera Corporation, San Jose, California, USA. All rights reserved.
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
// software and associated documentation files (the "Software"), to deal in the Software
// without restriction, including without limitation the rights to use, copy, modify, merge,
// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to
// whom the Software is furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in all copies or
// substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
// HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
// WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
// OTHER DEALINGS IN THE SOFTWARE.
//
// This agreement shall be governed in all respects by the laws of the State of California and
// by the laws of the United States of America.


#define ROWS 5
#define COLS 5


// Sobel filter kernel
// frame_in and frame_out are different buffers. Specify restrict on
// them so that the compiler knows they do not alias each other.
__kernel
void sobel(global int * restrict frame_in, global int * restrict frame_out,
const int iterations, const unsigned int threshold)
{
// Filter coefficients
int Gx[3][3] = {{-1,-2,-1},{0,0,0},{1,2,1}};
int Gy[3][3] = {{-1,0,1},{-2,0,2},{-1,0,1}};


// Pixel buffer of 2 rows and 3 extra pixels
int rows[2 * COLS + 3] = {0};


// The initial iterations are used to initialize the pixel buffer.
// int count = -(2 * COLS + 3);
int count=0;
while (count != iterations) {
// Each cycle, shift a new pixel into the buffer.
// Unrolling this loop allows the compile to infer a shift register.
#pragma unroll
for (int i = COLS * 2 + 2; i > 0; --i) {
rows[i] = rows[i - 1];
}
rows[0] = count >= 0 ? frame_in[count] : 0;


int x_dir = 0;
int y_dir = 0;


// With these loops unrolled, one convolution can be computed every
// cycle.
#pragma unroll
for (int i = 0; i < 3; ++i) {
#pragma unroll
for (int j = 0; j < 3; ++j) {
unsigned int pixel = rows[i * COLS + j];
unsigned int b = pixel & 0xff;
unsigned int g = (pixel >> 8) & 0xff;
unsigned int r = (pixel >> 16) & 0xff;


// RGB -> Luma conversion approximation
// Avoiding floating point math operators greatly reduces
// resource usage.
unsigned int luma = r * 66 + g * 129 + b * 25;
luma = (luma + 128) >> 8;
luma += 16;


x_dir += pixel * Gx[i][j];
y_dir += pixel * Gy[i][j];
}
}


int temp = abs(x_dir) + abs(y_dir);
unsigned int clamped;
if (temp > threshold) {
clamped = 0xffffff;
} else {
clamped = 0;
}


if (count >= 0) {
frame_out[count] = clamped;
}
count++;
}
}

how to create matrix in VHDL

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Hi guys! I am trying to create a matrix or an array. 4 columns and 2 rows. Is my code correct?

Code:

type row_t is array(0 to 3) of std_logic_vector(7 downto 0);
  type matrix_t is array(0 to 1, 0 to 3) of std_logic_vector(7 downto 0);

Also I want to assign a variable to the first column? what is the syntax for this? thank you.

displayport quad pixel mode

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Hi everyone,

i want to display a 2k video from a test pattern genarator module in to a display using display port. while configuring display port TX-pixel input mode to quad i found that 4 Hync 4 Vsync and 4 De signals are needed as input..but i have only one de hsync vsync signal from from my pattern generator. . my question is why there are 4 hsync 4 vsync and 4 de signal if i select quad pixel at display port tx input ? if my input is 4 pixels a clock why a single hsync vsync and de signals are not suffitient?

ALTLVDS Failing timing on simple interface

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Hi
I am failing timing implementing a simple ALTLVDS The clock speed is 200MHz the de-serialization factor is 2.
I am interfacing a CYCLONE V SOC system to a two channel, 14 bit ADC (ADS4249) ADC via LVDS I have 14 LVDS lanes in total to cover both ADC channels. Each lane does two bits.
My problem is that Timequest is failing on setup time.

I have not specified any constraints in my Timequest sdc for the LVDS.
I am using Quartus 14.1. I notice that the megawizard greys out nearly all the options as soon as I select a deserialization factor of 2. Is this because ALTLVDS does not use PLLs for de-serialisation factors of 2?

Please can anyone help me get my design through timing?
Thanks
Dave

On Chip Memory Configuration and Altera Megafunction

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Hi! I have a Cyclone V device that has 5,662,720 block memory bits.I have implemented 3 dual port RAMs that are 8 bits wide and 139520 deep.I figured that each RAM would amount to 109 M10K blocks, and I have tested the design in hardware and it seems to work.All three of these RAMs were inferred in code and no IP core was used.
I have a few questions though :
1) Why does the Altera Megafunction provide depth only in powers of 2 like 2048(2^11)... 32768(2^15) ... 65536(2^16)?
Is it only so that the memory can be fully addressed by a n-bit pointer?
2) Why doesn't it go beyond 65536? Especially when I can infer 3 dual port RAMs of 139520(not a power of 2) depth?
3) How to know what sort of memory has been inferred? M10K, M4K, M9K? The megafunction GUI allows you to specify but I think there's no such provision possible when you try to infer it in code.

By this point, the synthesis report shows that I am using 3,348,000/5,662,720 block memory bits (59 percent).

Now, I tried to infer 6 single port RAMs 1 bit wide & 69120 deep.The design doesn't synthesize and gives the following warning :
"Cannot convert all sets of registers into RAM megafunctions when creating nodes..."

I get the warning despite having Auto Ram Replacement turned ON(by default).


Strangely, when I try to infer the same amount of memory in a different configuration like 8 bits wide and 51840 deep, the design works.
Why is this so?
Which is a more efficient memory design? High depth or High Width?

Thank you!

simulating avalon conduit interface signal in modelsim

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Hello All,
I have some problems regarding simulating avalon conduit interface signal. I have designed a sequence detector which detects 3 bits sequence given by user. This detector has avalon mm interface with NIOS II Master. and also has conduit interface with a sequence generator module which generates random sequence of ones and zeros. I have imported the output signal of generator as a input signal of detector via avalon conduit interface. but the problem is I can not import the signal while simulation of design using Modelsim. It shows me red line. Can anyone help me out with this issue??? :confused:

I am attaching the code of avalon mm interface, detector and generator. Please review this also. If there is any issue, please do mention it.
Thank you.
Attached Files

Altera On-Chip Flash IP Core

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I've included Altera On-Chip Flash IP Core in my project. The core created a component
Code:

component flash_update is
        port (
            clock                  : in  std_logic                    := 'X';            -- clk
            avmm_csr_addr          : in  std_logic                    := 'X';            -- address
            avmm_csr_read          : in  std_logic                    := 'X';            -- read
            avmm_csr_writedata      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
            avmm_csr_write          : in  std_logic                    := 'X';            -- write
            avmm_csr_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
            avmm_data_addr          : in  std_logic_vector(18 downto 0) := (others => 'X'); -- address
            avmm_data_read          : in  std_logic                    := 'X';            -- read
            avmm_data_writedata    : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
            avmm_data_write        : in  std_logic                    := 'X';            -- write
            avmm_data_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
            avmm_data_waitrequest  : out std_logic;                                        -- waitrequest
            avmm_data_readdatavalid : out std_logic;                                        -- readdatavalid
            avmm_data_burstcount    : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- burstcount
            reset_n                : in  std_logic                    := 'X'              -- reset_n
        );
    end component flash_update;

    u0 : component flash_update
        port map (
            clock                  => CONNECTED_TO_clock,                  --    clk.clk
            avmm_csr_addr          => CONNECTED_TO_avmm_csr_addr,          --    csr.address
            avmm_csr_read          => CONNECTED_TO_avmm_csr_read,          --      .read
            avmm_csr_writedata      => CONNECTED_TO_avmm_csr_writedata,      --      .writedata
            avmm_csr_write          => CONNECTED_TO_avmm_csr_write,          --      .write
            avmm_csr_readdata      => CONNECTED_TO_avmm_csr_readdata,      --      .readdata
            avmm_data_addr          => CONNECTED_TO_avmm_data_addr,          --  data.address
            avmm_data_read          => CONNECTED_TO_avmm_data_read,          --      .read
            avmm_data_writedata    => CONNECTED_TO_avmm_data_writedata,    --      .writedata
            avmm_data_write        => CONNECTED_TO_avmm_data_write,        --      .write
            avmm_data_readdata      => CONNECTED_TO_avmm_data_readdata,      --      .readdata
            avmm_data_waitrequest  => CONNECTED_TO_avmm_data_waitrequest,  --      .waitrequest
            avmm_data_readdatavalid => CONNECTED_TO_avmm_data_readdatavalid, --      .readdatavalid
            avmm_data_burstcount    => CONNECTED_TO_avmm_data_burstcount,    --      .burstcount
            reset_n                => CONNECTED_TO_reset_n                  -- nreset.reset_n
        );

How should I use it to program CFM on MAX10? I need some example.

Quartus 17 JBC Files & STAPL Player @ MAX10

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Hi,

I recently installed Quartus 17.0.0 Build 595 and noticed that the JBC Files generated with this version do not work with our UEFI port of the STAPL player. It seems that player ignores the do_real_time_isp option. I found that Quartus 17 is using ALG_VERSION 68 compared to 16.x, which was using ALG_VERSION 67. Additionally, the generated JBC Files are much larger than with previous versions, even though compression is enabled. Has anyone seen similar issues and what could be the reason?

Thanks & Regards
Tiano

P.S. Just proofed that the same happens with quartus_jli.exe and the Quartus programmer GUI (I'm using USB Blaster). With .pof files, Real-time ISP works fine.

matrix array in vhdl

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Hello. I want to access a certain element in an array and place a value in it. What is its syntax? Here is my array.

Code:

TYPE VOQ_ROW IS ARRAY (O TO 4) OF STD_LOGIC_VECTOR(3 DOWNTO 0);
TYPE VOQ_MATRIX IS ARRAY(O TO 1) OF VOQ_ROW;

Port "out1" does not exist in primitive "AND2" of instance "STEP3"? (Code inside)

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Hey guys,

So I am kind of confused by this error. A quick generic google search got me on another thread in this forum where someone else was facing this problem and when he changed his entity name it was working but I tried changing AND2 to AND3 and the issue persisted. There are no other entities with the name AND2 and I am not importing any files whatsoever. Here is the full code:

Code:

LIBRARY ieee;USE ieee.std_logic_1164.all;


ENTITY ALU1bit IS
    PORT (A,B,InvertA,InvertB,CarryIn :IN STD_LOGIC;
            Operation                        :IN STD_LOGIC_VECTOR(1 DOWNTO 0);
            Result,CarryOut                              :OUT STD_LOGIC);
END ALU1bit;


ARCHITECTURE ARCH1 OF ALU1bit IS
    COMPONENT XOR2 IS
        PORT(in1,in2 :IN STD_LOGIC;
              out1      :OUT STD_LOGIC);
    END COMPONENT;
    COMPONENT AND2 IS
        PORT(in1,in2 :IN STD_LOGIC;
              out1    :OUT STD_LOGIC);
    END COMPONENT;
    COMPONENT OR2 IS
        PORT(in1,in2 :IN STD_LOGIC;
              out1    :OUT STD_LOGIC);
    END COMPONENT;
    COMPONENT FULLADDER IS
        PORT(in1,in2,in3 :IN STD_LOGIC;
              out1,out2  :OUT STD_LOGIC);
    END COMPONENT;
    COMPONENT OPERATION_EVAL IS
        PORT(in1,in2,in3,in4 :IN STD_LOGIC;
              in5                    :IN STD_LOGIC_VECTOR(1 DOWNTO 0);
              out1                    :OUT STD_LOGIC);
    END COMPONENT;
    SIGNAL AInverted, BInverted, aANDb, aORb, aXORb, Sum : STD_LOGIC;
BEGIN
    STEP1 : XOR2 PORT MAP (A,InvertA,AInverted);
    STEP2 : XOR2 PORT MAP (B,InvertB,BInverted);
    STEP3 : AND2 PORT MAP (AInverted,BInverted,aANDb);
    STEP4 : OR2 PORT MAP (AInverted,BInverted,aORb);
    STEP5 : XOR2 PORT MAP (AInverted,BInverted,aXORb);
    STEP6 : FULLADDER PORT MAP (AInverted,BInverted,CarryIn,Sum,CarryOut);
    STEP7 : OPERATION_EVAL PORT MAP (aANDb,aORb,aXORb,Sum,Operation,Result);
END ARCH1;


LIBRARY ieee;
USE ieee.std_logic_1164.all;


ENTITY XOR2 IS
    PORT (in1,in2 :IN STD_LOGIC;
            out1      :OUT STD_LOGIC);
END XOR2;


ARCHITECTURE ARCH2 OF XOR2 IS
BEGIN
    out1 <= in1 XOR in2;
END ARCH2;


LIBRARY ieee;
USE ieee.std_logic_1164.all;


ENTITY AND2 IS
    PORT (in1,in2 :IN STD_LOGIC;
            out1      :OUT STD_LOGIC);
END AND2;


ARCHITECTURE ARCH3 OF AND2 IS
BEGIN
    out1 <= in1 AND in2;
END ARCH3;


LIBRARY ieee;
USE ieee.std_logic_1164.all;


ENTITY OR2 IS
    PORT (in1,in2 :IN STD_LOGIC;
            out1      :OUT STD_LOGIC);
END OR2;


ARCHITECTURE ARCH4 OF OR2 IS
BEGIN
    out1 <= in1 OR in2;
END ARCH4;


LIBRARY ieee;
USE ieee.std_logic_1164.all;


ENTITY FULLADDER IS
    PORT (toAdd1,toAdd2,CarryIn :IN STD_LOGIC;
            Sum,CarryOut            :OUT STD_LOGIC);
END FULLADDER;


ARCHITECTURE ARCH5 OF FULLADDER IS
BEGIN
    Sum <= (toAdd1 AND (NOT toAdd2) AND (NOT CarryIn)) OR ((NOT toAdd1) AND toAdd2 AND (NOT CarryIn)) OR ((NOT toAdd1) AND (NOT toAdd2) AND CarryIn) OR (toAdd1 AND toAdd2 AND CarryIn);
    CarryOut <= (toAdd1 AND CarryIn) OR (toAdd2 AND CarryIn) OR (toAdd1 AND toAdd2);
END ARCH5;


LIBRARY ieee;
USE ieee.std_logic_1164.all;


ENTITY OPERATION_EVAL IS
    PORT (Operation1,Operation2,Operation3,Operation4 : IN STD_LOGIC;
            OpCode                                                  : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
            Final                                                    : OUT STD_LOGIC);
END OPERATION_EVAL;


ARCHITECTURE ARCH6 OF OPERATION_EVAL IS
BEGIN
    WITH OpCode SELECT
        Final <= Operation1 WHEN "00",
                    Operation2 WHEN "01",
                    Operation3 WHEN "10",
                    Operation4 WHEN OTHERS;
END ARCH6;

Avalon-MM burst mode uniphy

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Hello! I try to use altera reference disign multiport frontend with different burst size in ports;
I dont completely understand how works burst addressation.
For example : i use data wingth 256 bit => master_addr = {user_addr,5'b0};

i write burstsize = 2 in address =7 => master_addr = 00E0; data - d(1)='.....e1' d(2)='....e2' byteenable = ffffffff;
how i understand in this case d(1) write in addr=7 (00E0) and d(2)write in addr =8(0100)? correct?


after that a write burstsize = 1 in addr = 8 data - 'e6'

after that i read burstsize = 2 in addr = 7 and i get 'e1' 'e2'. I thought i will get 'e1' 'e6'. where i wrong?
Attached Images

Cannot find specific errors of kernel compilation

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I'm trying to compile a specific kernel I've written myself. The compilation fails while it tries to generate the hardware implementation. It also fails after one hour processing, with no reason. It's most probably cannot synthesis the model, but I cannot find any related log file explains what exactly is happening. Here is my kernel:


Code:

__kernel void Test51(__global double *data, __global double *rands, int index, int rand_max){


    double2 temp;
    int gid = get_global_id(0);


    temp = data[gid];
    temp = (double) rands[1] * temp;
    temp = (double) rands[2] * temp;
    temp = (double) rands[3] * temp;
    temp = (double) rands[4] * temp;
    temp = (double) rands[5] * temp;
    temp = (double) rands[6] * temp;
    temp = (double) rands[7] * temp;
.....

    temp = (double) rands[493] * temp;
    temp = (double) rands[494] * temp;
    temp = (double) rands[495] * temp;
    temp = (double) rands[496] * temp;
    temp = (double) rands[497] * temp;
    temp = (double) rands[498] * temp;
    temp = (double) rands[499] * temp;
    data[gid] = temp.s0;


}

I've tried so hard to understand what exactly is the reason for failure but cannot figure out anything. Can anyone help me with this issue?

Testbench

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Hi everyone
I need to help for my graduate thesis. I am working on aes 128 cipher and i had a code but i need a simulation and testbench . how can i do them . pls help me . I appretiated for your advice and help
I hope I could tell you thanks.

older vip documentation ug_vip.pdf

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Hi, where can i find older documentation files for vip suite? the link provided in IPcore information contains version updated to 17.0. I need to review design with 14.0 version ipcores. Regards.

DE0-Nano-SoC Kit, Route ETH pins to FPGA?

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Hello,

Regarding Terasoc's product, http://www.terasic.com.tw/cgi-bin/pa...English&No=941

I'm considering making a tiny little thing where Ethernet/UDP communication is time-critical, handled by the FPGA and not the HPS component.
The DE0-Nano-SoC looks ideal, except I really dont need the ARM CPU...

Does anyone know if the board supports routing the ENET pins to the FPGA directly?


Grateful for any feedback on this, guys :)


With Best Regards,
Stride

“HSSI_REFCLK_CLUSTER” error on Arria 10

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If you run into errors with “HSSI_REFCLK_CLUSTER” when compiling for Arria 10, check if you are using an fPLL to drive core logic. If so, try inserting a clock buffer (ALTCLK_CTRL) between your input pin and the fPLL.
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