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ALTPLL Design Example

May 23, 2017, 8:32 am
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Hello everyone

I am trying to find an507_altpll_dynphase_de2.zip design example. apparently, it has been removed from Altera website. can someone show me where I can find this design example. the design example is about Implementing PLL Reconfiguration in Cyclone III Devices

thanks in advance
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Questions about SOC FPGA Preloader and device tree

May 23, 2017, 3:40 pm
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Hi

I’m working on a project using the Terasic Spider robot which uses the DE0 NANO SOC board. It is a Cyclone 5 board.
I’m building a Metal Detection application on top of the spider and I’m using the Terasic Spider reference Designs.
I added ADC IP component to the QSYS system and wire it to the HPS system then I compiled the design, copied the .rbf file to the SD card. Then I generated the header files (HPS_0.h) and replaced it with the old one in the Linux program reference design.
Thankfully, I was successful to build my application on top of the board. However, The spider movement stopped at all or sometimes behave weirdly.
from what I read online, I’m guessing that I have to recompile the preloader or the device tree.
My question is what is wrong with my development flow, and what else should I recompile? the preloader or the device tree or both?

Thanks.
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Quartus II Web Edition 13.1.0.162 Installation window not responding

May 23, 2017, 3:41 pm
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Hello Everyone,

This is my first post in this forum. If you happen to find any corrections to be made to this post, please let me know.

I recently downloaded the Quartus II Web edition version 13.1.0.162 and installed it. However during installation towards the end, the installation window froze and displays "not responding" on the title bar. It does not seem to solve on its own. Is there any fix for this problem.

However, the installation also involved installing the ModelSim-Altera 10.1d (Quartus II 13.1). This application is available and is running fine. But the installation window has frozen. I am attaching a screenshot of my how my window looks after the freeze. Can anyone help me on this?

I had installed the Quartus II 9.0 version before and uninstalled it during the installation of the 13.1 version. Could this be the source of the window staying in the freeze state?

Sincerely,
Ritesh
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Progress stops during compilation

May 23, 2017, 5:20 pm
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I have installed Quartus pro version 17.0, along with Altera OpenCL version 17.0, and I am attempting to compile the example projects (hello_world, vector_add).

I have followed as many threads as I could regarding this issue, but none have solved the problem yet.

My environment variables are set the following way:



export PATH=$PATH:/root/intelFPGA_pro/17.0/quartus

export PATH=$PATH:/root/intelFPGA_pro/17.0/quartus/bin
export QUARTUS_ROOTDIR=/root/intelFPGA_pro/17.0/quartus

export AOCL_BOARD_PACKAGE_ROOT=/root/intelFPGA_pro/17.0/hld/board/a10_ref

export ALTERAOCLSDKROOT="/root/intelFPGA_pro/17.0/hld"

export PATH=$PATH:/root/intelFPGA_pro/17.0/qsys/bin
export QSYS_ROOTDIR="/root/intelFPGA_pro/17.0/qsys/bin"
export PATH="$ALTERAOCLSDKROOT/bin":$PATH

export LD_LIBRARY_PATH="ALTERAOCLSDKROOT/host/linux64/lib":$LD_LIBRARY_PATH

export LD_LIBRARY_PATH="AOCL_BOARD_PACKAGE_ROOT/linux64/lib":$LD_LIBRARY_PATH

export QUARTUS_ROOTDIR_OVERRIDE=/root/intelFPGA_pro/17.0/quartus


"aocl diagnose" passes, and compiling with the "march=emulator" is successful.

When doing a full compilation, the progress stops. The hello_world.aoco file is generated, but not hello_world.aocx. Log files no longer update, and the compilation doesn't progress even after hours of running.



The hello_world.log file is attached. prior to stopping the compilation, these is the final entries (when progression is stopped) in hello_world.log:



Info: qsys-generate -syn --family="Arria 10" --part=10AX115S2F45I1SG kernel_system.qsys

Info (23030): Evaluation of Tcl script scripts/pre_flow_pr.tcl was successful

Info: Quartus Prime Shell was successful. 0 errors, 0 warnings

Info: Peak virtual memory: 968 megabytes

Info: Processing ended: Tue May 23 17:44:15 2017

Info: Elapsed time: 00:00:34

Info: Total CPU time (on all processors): 00:01:27


I can provide any additional information if needed.

Thank you.
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Windows 10 driver support for USB Blaster ?

May 23, 2017, 6:19 pm
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In reviewing the drivers download page it appears there are NO drivers for Windows 10 for the USB based Blaster programmer cables.

Is this really true ?
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Got CL_INVALID_BINARY error when emulated HelloWorld example on Windows

May 23, 2017, 7:35 pm
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I followed the "aocl_getting_started.pdf" instruction to implement the hello_world example on Window. But I got error message about CL_INVALID_BINARY when I tried to run the emulator.


The steps that I've done are as following:


1. "%ALTERAOCLSDKROOT%\init_opencl.bat", set environment.


2. "aoc -march=emulator -v --board s5_ref device/hello_world.cl -o bin/hello_world.aocx", built hello_world.aocx file successlly.


3. "set CL_CONTEXT_EMULATOR_DEVICE_ALTERA=1 host.exe"


4. Built host program(host.exe) from Visual Studio 2010 successlly.


5. Under folder hello_world\bin. Run host.exe on cmd, and get the error message as the image in the attachment.

Using AOCX: hello_world.aocx
Context callback: Invalid binary.
ERROR: CL_INVALID_BINARY
Location: ..\common\src\AOCLUtils\opencl.cpp:392
Failed to create program with binary

Is there any step I missed? Please advice.
Thank you.
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addressing in Nios II processor

May 23, 2017, 10:09 pm
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Hello all,
I want to know about dynamic and native addresses and their alignment in Nios II processor. I do not understand how these addresses are used and incremented for addressing any location in processor and memory. How do I calculate offset for a particular address. Which one is more efficient ? Dynamic or Native?
Can any one please help me in resolving this issue? :confused:
Thank You.
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Board support package of Cyclone V GT Kit for OpenCL for window

May 23, 2017, 4:00 pm
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Hi

I'm trying to get OpneCL working on Cyclone V GT (not Soc).
However the OpenCL SDK by Altera doesn't include the board support for Cyclone V GT.
I found someone made the support package on Alterawiki, but it's made for Linux, and I couldn't get the driver working on my Ubuntu.
Can anyone give me advise on how to generate the package for window64?

Thank you.
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88e1111 phy

May 23, 2017, 11:14 pm
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I have designed Cyclone V FPGA based board.

When i try to program, initial configuration is not working in Ethernet PHY.

Can't see any LED glowing in Ethernet PHY.

Hereby I have attached Ethernet PHY schematic.

Please verify and guide me to clear this issue.
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A question about the toggle in early power estimation (EPE)

May 24, 2017, 12:58 am
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Hi
I have used the EPE tool based on excel. I cannot determine the value of the toggle. I have some questions about the toggle values. Are the toggle values in the "Logic", "Ram", "DSP", "IO" the same or different? How much are the proper values for these terms?

Thank you
Haoxinyu
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GPIO Expansion Header pinout for De1-SOC and De10 standard boards

May 24, 2017, 1:07 am
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Hello,
I'm looking for complete pinot of GPIO Expansion Header for De1-SOC and De10 standard boards.
Every header has 40 pins, all data I've found describes only 36 pins of GPIO. Which pins are 5V & GND , 3.3V and GND? for both boards.
Thank you.

"...It comes with with DC +5V (VCC5), 3.3V VCC3P3), and two GND" - from DE10- Standard User manual , page 26
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How to use Altera BRAM instance as a DualPort RAM with 1 Write and 2 parallel reads

May 24, 2017, 2:14 am
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Hi,

I had used altsyncram for writing into first port and reading from the second port in a DUAL_PORT mode. Everything seems to be working in the simulation and in the hardware. Now the design changes demand writing data into PortA, and ability to read simultaneously from PortA and from PortB. I modified the altsyncram configuration to make it BIDIR_DUAL_PORT with the following instance usage


altsyncram #(
.address_aclr_b ("CLEAR0" ),
.intended_device_family ("Stratix V" ),
.lpm_type ("altsyncram" ),
.numwords_a (DATA_DEPTH ),
.numwords_b (DATA_DEPTH ),
.operation_mode ("BIDIR_DUAL_PORT" ), // Single Port Access
.outdata_aclr_b ("CLEAR0" ),
.power_up_uninitialized ("TRUE" ),
.ram_block_type ("M20K" ),
.read_during_write_mode_mixed_ports ("OLD_DATA"),
.widthad_a (ADDR_WIDTH ),
.widthad_b (ADDR_WIDTH ),
.width_a (1 ),
.width_b (1 ),
.width_byteena_a (1 )
)
altsyncm20k_mask
(.aclr0 (1'b0 ),
.address_a (maskindex_ff),
.clock0 (clk ),
.data_a (maskin_ff),
.wren_a (wr_ff),
.address_b (cam_index_ff),
.aclr1 (1'b0 ),
.addressstall_a (1'b0 ),
.addressstall_b (1'b0 ),
.byteena_a (1'b1 ),
.byteena_b (1'b1 ),
.clock1 (clk ),
.clocken0 (1'b1 ),
.clocken1 (1'b1 ),
.clocken2 (1'b1 ),
.clocken3 (1'b1 ),
.data_b (1'b0 ),
.eccstatus ( ),
.q_a (maskstatusoutHost ),
.q_b (maskstatusouttbt),
.rden_a (lookupdirect_ff&~wr_ff),
.rden_b (cam_match_ff&lookuptbt_ff),
.wren_b (1'b0 )
);


Surprisingly the simulation gives valid reads from both the ports, but in hardware the readdata from PortB isnt valid, but readvalue from PortA is correct.

1) What could be the reason why read on PortB fails in hardware. I went through the https://www.altera.com/ja_JP/pdfs/li...ug_ram_rom.pdf, but couldnt make out any mistakes.

2) Whats the difference between altsyncram and altdpram(UseCase) ?.


References: FPGA Used: StratixV
ADDR_WIDTH:11
DATA_DEPTH:2048


Thanks in advance
Jeebu Jacob Thomas
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Error during QSYS generation

May 24, 2017, 2:59 am
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I'm getting strange error during generation of system with DDR2 controller

Error: GenerateSim: Could not move C:\Users\WAT\AppData\Local\Temp\alt7310_6655338575 060564170.dir\0001_iptb_gen\DRAMsystem_altmemddr_0 _mem_model.v to C:\Users\WAT\AppData\Local\Temp\alt7310_6655338575 060564170.dir\0001_iptb_gen\testbench\DRAMsystem_a ltmemddr_0_mem_model.v

system is minimal, it has only clock bridge and entrance from external bus.
I generate only system, no simulation files.

I can see some files being generated in the said folder, but the compilation stops on this file.

Problem persists in Q16.1 and Q17

Earlier versions of system (more complicated) with this IPcore were generated successfully in Q13 I guess. (i changed computer and don't have all archives now)

Can You generate system with DDR2 in Your newest quartusses?
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Error(11999): Channel(s) under reference clocks - arria 10 development kit design

May 24, 2017, 6:03 am
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I'm designing a system on an Arria 10 development kit which uses the FMC connectors as I/O, and have assigned pins according to the user guide. The design passes analysis and synthesis, however I receiving this error on the fitting stage of compilation:

Error(11999): Channel(s) under reference clocks: are 50 tx channels, 0 rx channels, which exceeds the capacity for the targeted device's HSSI strip, 36 channels.

Any ideas on why this is the case if this board has been designed in the this way, or ideas on how to rectify this?
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Best practice to define bidirectional pin in top level design file with Quartus II?

May 24, 2017, 4:55 am
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Being new to Quartus II and still in the phase to build some simple tests
I used the Pin planner to define a bidirectional pin.

This resulted in the following top level design file test1_top.v:

Code:

    module test1_top
    (
        IO1
    );

    inout IO1;

    endmodule
Compiling this leads to the following warning:

Warning (169064): Following 1 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may
change fitting results Info (169065): Pin IO1 has a permanently disabled output enable

Now I added another node 'IO1_OE' (also using pin planner):


Code:

    module test1_top
    (
        IO1,
        IO1_OE
    );

    inout IO1;

    assign IO1 = (IO1_OE == 0) ? 1'b1 : 1'bZ;

    endmodule
But now I get the following warning:

Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 2 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.

So the final question is: How do I correctly create (and use) a bidirectional pin in the top level module using Quartus?
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Powerplay Result

May 24, 2017, 8:37 pm
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Hi,I have generated a .vcd file and insert it into the Powerplay Power Analyzer Tool in Quartus II 11.0,and get the result as follow. I think the dynamic power is too small. IS THIS RESULT CORRECT?

And I think there may be sth wrong about the clock, I show the warnings in the following and HOW CAN I CORRECT IT.


thanks sincerely.
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Issue with POS-PHY level 4 megacore

May 25, 2017, 1:17 am
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Hi,
I'm using quartus 10.1 sp_1 version. I just instantiated POS_PHY level 4 megacore function. After I generate the IP core, It gives following files.

1. *_tx_core.v2. *_tx_modules.v
3. *_altfifo_concat.v
4 *.v
5 *_tx_data_proc.ocp
6 *.sdc
and all submodules.

The issue is in *_tx_core.v file. In this files there are reset_syncer and *_altfifo_atltop instants.when i start compilation i got error as *_reset_syncer & *_altfifo_atltop module not found.

when i create the IP core, it should generate all required *.v files, but in my case these two files are missing.


thanks in advance
Vinod
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DDR3 SDRAM controller with Uni PHY, DMA and external UART(RS232) qsys implementation

May 25, 2017, 5:04 am
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Hi,
I am using MAX 10 FPGA development board (package : 10M50DAF484C6GES). I'm planning to test the memory_test (includes memory test, DMA and FLASH) application in NIOS II. I made a qsys design to test the memory and DMA. I used external UART (RS232) to print the output (I didn't use JTAG UART). I'm using putty as serial terminal. After downloading the .elf on hardware it was stucking. I'm not able to type anything on putty. I'm adding qsys design. If any mistakes is there please let me know.

Thanks in advance.

Regards,
Vijji
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My first FPGA

May 25, 2017, 5:39 am
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Y have a problem with simple counter, becouse my FPGA design won't work. Y did everithing as you demonstrate, but when Y try to implement it on board (in autodetect) VTAP10 goes serial and design won't work (without VTAP10 it won't implement on board) my contact is stefan.pendic94@gmail.com
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Max10 Eval Kit User Flash Memory IP

May 25, 2017, 8:00 am
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Hey everyone, I've been trying
As a sidenote - I have read the MAX10 User Flash Memory guide in its entirety no fewer than 3 times, however, I have almost zero experience in verilog.

I'm trying to use the push buttons on my development kit to "one step" my way through the Altera Flash IP core, and reading out significant signals to the leds on board as a troubleshooting tool. My problem is currently, I try to write to the CSR control register, then read back the CSR control register to verify my changes went though - they never do. Any guidance as to where to go from here (or if I'm completely off course..) would be greatly appreciated. Here's my verilog code. Thanks!

module FlashMemory(
clock,
pbs,
led
);


input clock;
input [3:0]pbs;
output [4:0]led;


/////////////////////////
reg[31:0] writedata = 32'h00000000;
reg[31:0] readdata;
reg[15:0] dataaddress = 16'h0004;


reg[31:0] readdatacopy = 32'hFFFFFFFF;


reg datawrite = 1'b0;
reg dataread = 1'b0;
reg burstcount = 1;
reg busy;
/////////////////////////
reg[31:0] csrwritedata = 32'h001FFFFF;
reg[31:0] csrreaddata;
reg[15:0] csraddress = 16'h0001;


reg csrhighbit = 1'b1;


reg csrwrite = 1'b0;
reg csrread= 1'b0;
/////////////////////////
reg reset;
wire pllclock;
wire locked;
wire readdataok;
reg [4:0]led = 5'b11111;


reg writebutton;
reg readbutton;
reg csrwritebutton;
reg csrreadbutton;
reg csrwriteprotection;
reg dummy = 1'b0;
reg [31:0] writetimer = 0;


always @(posedge pllclock) begin


if(dummy)begin
reset <= 1'b0;
end
/////////////////////////
else begin
reset <= 1'b1;


csrwritebutton <= pbs[0];
csrwriteprotection <= pbs[1];
csrreadbutton <= pbs[2];




if(!pbs[0] && csrwritebutton)begin
csrwritedata <= 32'h001FFFFF;
csrwrite <= 1'b1;
end else if(!pbs[1] && csrwriteprotection) begin
csrwritedata <= 32'hFFFFFFFF;
csrwrite <= 1'b1;
end else begin
csrwrite <= 1'b0;
end


if(!pbs[2] && csrreadbutton) begin
csrread <= 1'b1;
end else begin
csrread <= 1'b0;
end


if(!csrreaddata[31]) begin
csrhighbit <= csrreaddata[31];
end


if (csrread) begin
led[0] <= 1'b0;
end


if (csrhighbit)begin
led[4] <= 1'b1;
end
if (!csrhighbit)begin
led[4] <= 1'b0;
end




end
end
FlashIP FlashIP_inst (
.clock (pllclock), // clk.clk
.reset_n (reset), // nreset.reset_n
.avmm_data_addr (dataaddress), // data.address
.avmm_data_read (dataread), // .read
.avmm_data_writedata (writedata), // .writedata
.avmm_data_write (datawrite), // .write
.avmm_data_readdata (readdata), // .readdata
.avmm_data_waitrequest (busy), // .waitrequest
.avmm_data_readdatavalid (readdataok), // .readdatavalid
.avmm_data_burstcount (burstcount), // .burstcount
.avmm_csr_addr (csraddress), // csr.address
.avmm_csr_read (csrread), // .read
.avmm_csr_writedata (csrwritedata), // .writedata
.avmm_csr_write (csrwrite), // .write
.avmm_csr_readdata (csrreaddata) // .readdata
&nbsp;);






FlashPLL FlashPLL_inst (
.inclk0 ( clock ),
.c0 ( pllclock ),
.locked ( locked)
&nbsp;);




endmodule
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