Quartus II V16: .sdo files not generated

July 18, 2017, 7:48 pm

≫ Next: Cascaded Interpolation Filter and Restricted Fmax

嗨，
我有一個問題，
在Quartus II V16.1 Build 196，5CGTFD9E5F35C7 Cyclone V，Verilog，我不能得到任何.sdo文件。
我檢查編譯報告 - > EDA Netlist Writer - >生成的文件，只生成vo文件。不是sdo。
如何為cyclone v設備生成.sdo文件。

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Cascaded Interpolation Filter and Restricted Fmax

July 19, 2017, 2:32 am

≫ Next: Power Management in Cyclone V SOC

≪ Previous: Quartus II V16: .sdo files not generated

Hallo

For my design i am using Simulink and HDL coder from MATLAB to generate the HDL code. Then i use the Altera Quatras II to synthesize and generate the programming file for my DE0-NANO development kit board with cyclone V (EP4CE22F17C6).
I am trying to make an interpolation filter of 256 Up sampling. But this is too big for the HDL coder to generate the code. To solve that problem i used one interpolation filter with 32 up sample and other one with 8 up sample. Then i cascaded the two filters to get the desired 256 up sampling. Now the problem starts with Restricted Fmax when i try to generate the HDL code for this model. When i generate HDL code for 32 up sample and 8 up sample separately without cascading them together both of them have a Fmax around 50 MHz. But when i cascade them and generate the HDL code for the model the Fmax comes down to 35 MHz. Whats is the reason behind this? Is there any optimization i can apply to increase the Fmax. I know clock optimization will increase the area, but that's now an concern right now.

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Power Management in Cyclone V SOC

July 19, 2017, 3:51 am

≫ Next: how to set values in the same register in the PL side

≪ Previous: Cascaded Interpolation Filter and Restricted Fmax

Hi Altera Team,

We would like to whether all the power reduction techniques for HPS listed in the below link is implemented on bare metal(Power_optimisation.zip) for Cyclone V SOC development kit?
https://www.altera.co.jp/documentati...135565764.html

Various methods discussed in the link are listed below:

HPS Method 1: Fit Code in Cache
HPS Method 2: Processor Standby Modes and Dynamic Clock Gating
HPS Method 3: CPU1 in WFI/WFE or Standby Loop
HPS Method 4: Suspend to RAM/SDRAM self refresh or Suspend to Disk
HPS Method 5: Lowering CPU Frequency
HPS Method 6: Energy Efficient Ethernet
HPS Method 7: USB Power Management
HPS Method 8: Unused Peripherals in Reset

Please confirm.

Thanks in advance

Rabiammal A

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how to set values in the same register in the PL side

July 19, 2017, 4:56 am

≫ Next: PLL is not working in Cylcone V GX (Using Integer PLL)

≪ Previous: Power Management in Cyclone V SOC

Hello
I have flags that I set from my PS soc. Know to read them from PL side I have an implementation error when I use the same register !

Code:

 test1 <= slv_reg3(31);

    test2 <= slv_reg3(30);

    PSenable <= slv_reg3(29);

the error :

Attached Images

Untitled.jpg (22.7 KB)

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PLL is not working in Cylcone V GX (Using Integer PLL)

July 19, 2017, 5:19 am

≫ Next: How to generate two non overlapping clock signals from single clock?

≪ Previous: how to set values in the same register in the PL side

Hi,
I have designed Customised board using Cyclone V GX FPGA.

I have fed 25MHz oscillator to non-dedicated clock pin in FPGA.

So i had incorporated ALCLKCTRL.

The design flow 25MHz -> altclkctrl ip -> altpll

In this case pll not locked and therefore no pll output

I have attached schematic file.

Please support.

Attached Images

Capture.jpg (18.9 KB)
power_circuitry.jpg (18.7 KB)

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How to generate two non overlapping clock signals from single clock?

July 19, 2017, 8:00 am

≫ Next: Timequest Timing Problems

≪ Previous: PLL is not working in Cylcone V GX (Using Integer PLL)

In a design I'd like to use both edges of an external clock signal (EXT_CLK).
No other clock signals are available. Now the question:

Is it possible to generate two signals

CLK1 == EXT_CLK and
CLK2 == !EXT_CLK

such that both signals are not high at the same time and such that
the resulting verilog code is not device/architecture specific?

Please excuse if this is a dumb question.

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Timequest Timing Problems

July 19, 2017, 8:20 am

≫ Next: Looking for free IPs

≪ Previous: How to generate two non overlapping clock signals from single clock?

Hi everyone,

I got problems when i was using Timequest.

My clock name is CLK, but quartus told my that "Warning (332060): Node: CLK~reg0 was determined to be a clock but was found without an associated clock assignment."

Is there anybody can help me ?

Thank you very much!

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Looking for free IPs

July 19, 2017, 8:28 am

≫ Next: Quartus II Programmer - Command Line

≪ Previous: Timequest Timing Problems

Hi,

I am new to Altera forum and Altera FPGAs in general. I have the following queries pls.

** Like Xilinx Core generator, does Altera Quartus 2 give free IPs as well? If so, what is the name of the core generator interface and is there a list of free IPs (preferably in VHDL) which one can
use?

** What is the difference between web edition and pro edition.

Thanks,

Arvind Gupta

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Quartus II Programmer - Command Line

July 19, 2017, 8:44 am

≫ Next: Max10 10m25 dual supply; jtag volatge

≪ Previous: Looking for free IPs

Hi,
Using the Quartus II Programmer command line (quartus_pgm app) to program a serial flash device using the USB ByteBlaster and want to first erase the full flash device, so planning to use -erase-all option, but want to ensure the usage is correct:

Altera Programmer V13.0sp1

C:\altera\13.0sp1\qprogrammer\bin>quartus_pgm -c usb-blaster -m JTAG -o p;C:\altera\13.0sp1\qprogrammer\common\devinfo\pro grammer\sfl_ep3c55.sof

Method 1: would use erase all in a command separate and prior to programming
C:\altera\13.0sp1\qprogrammer\bin>quartus_pgm -c usb-blaster -m JTAG -erase_all -o r;myFile.jic

Method 2: would use erase all command as part of programming command
C:\altera\13.0sp1\qprogrammer\bin>quartus_pgm -c usb-blaster -m JTAG -initcfg -erase_all -o bpv;myFile.jic

Thanks
Bill

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Max10 10m25 dual supply; jtag volatge

July 19, 2017, 9:21 am

≫ Next: FPGA to HPS (AXI Slave) address range issue

≪ Previous: Quartus II Programmer - Command Line

I'm working on a schematic with a 10M25DAF256I7G.
I'm going to power the FPGa with supply scheme as stated on Pin Connection Guide Line page 20:

VCC: 1.2V
VCCINT: 1.2V
VCCD_PLL: 1.2V
VCCA:2.5V
VCCA_ADC:2.5V
VCCIO:3.3V

I have a problem to understand the JTAG pull-up voltage.
As stated on Pin Connection Guide Line: "For configuration voltage of 2.5V, 3.0V or 3.3V, connect this pin through a 10kOhm resistor to 2.5V (VCCIO Bank 1 B) to prevent voltage overshoot..."
But my VCCIO is 3.3V for all banks. Why it says 2.5V?

Furthermore in the MAX10 Configuration User guide on page 3-3 the pull resistor are at VCCIO Bank 1B with clamp diode. So i think i can pull-up to 3.3V.

My question is:
If i use a configuration scheme as stated on page 20 of the Pin Connection Guide Line, how do i have to connect the jtag pull-up resistor for JTAG signals? Is it 2.5V or 3.3V with diode as stated in the Connection guide line?

Thanks

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FPGA to HPS (AXI Slave) address range issue

July 19, 2017, 10:04 am

≫ Next: memory initialization problem for 10M08SCU169C8G

≪ Previous: Max10 10m25 dual supply; jtag volatge

Hi People,
The Background : Part Cyclone V, Tools Q17, QSys
Task: To connect a MM Master Peripheral to write to Slave AXI of HPS

I'm using QSys (staring from a DE10_NANO_SoC_GHRD example) and want to be able to write from an external IP to the SDRAM via HPS.

The f2h_axi_slave interface has a range 0x0000_0000 to 0xFFFF_FFFF (and apparently I can't change it the range not sure why)
The master is an "External Bus to Avalon Bridge" with address range of 1MB (0x0000_0000 to 0x000F_FFFF)

when I try to connect the master avalon with the Slave AXI (I hope this is legal in Qsys) I get an error which sounds rather funny

Error: soc_system.bridge_0.avalon_master: hps_0.f2h_axi_slave (0x0..0xffffffff) is outside the master's address range (0x0..0xfffff)

let's not blame the tools yet, hence the question: I'm doing something fundamentally wrong here?

Thanks,
Aurash

PS - data width of both HPS AXI Slave and "External Bus to Avalon Bridge" is matched (128 bits)

PS2 - I just tried to connect the "External Bus to Avalon Bridge" (Master) to f2h_sdram0_data (Avalon Memory Slave) but I'm getting the exact same error - my guess is that the address bus width has to be matched between the two. (not sure how)

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memory initialization problem for 10M08SCU169C8G

July 18, 2017, 4:09 am

≫ Next: SignalTap fails timing often

≪ Previous: FPGA to HPS (AXI Slave) address range issue

we are trying to initialize M9k ROM with hex file for 10M08SCU169C8G device. the ROM is generated using IP Catlog. but tool is giving error
"Error (16031): Current Internal Configuration mode does not support memory initialization or ROM. Select Internal Configuration mode with ERAM."
please suggest some answer which will solve our problem

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SignalTap fails timing often

July 18, 2017, 7:24 am

≫ Next: Arria 10 Hard IP Pcie Bar configurations

≪ Previous: memory initialization problem for 10M08SCU169C8G

Hello,

I have the following problem: When I try to use SignalTap to peek on some of my signals, it often shows values which are not sensible, which is often the result of timing violations between my module and the SignalTap module. I have once manually constrained these paths(with set max delay), and it worked afterwards, but I wouldn't want to do this every time I want to peek somewhere else in my design or when I make significant changes. The SignalTap nodes are generated automatically, so I would have to look at TimeQuest every time and see whether some new register has popped up in SignalTap by my changes.
I am sampling with a clock rate of 62.5MHz on a Cyclone V, so it isn't even that fast for the device.
Is there a way to make the SignalTap automatically constrain the paths it needs?

Have a nice day,

Tibor

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Arria 10 Hard IP Pcie Bar configurations

July 18, 2017, 7:37 am

≫ Next: How to disable I/O Bank Source Voltage

≪ Previous: SignalTap fails timing often

I want configure an endpoint AV memory mapped Pcie Hard Ip Gen2 x1 in a Qsys System.
I need a suggestion as Bar blocks should be configured. I see an error bar0 size of 0 - bit is less than 4 altera pcie error .
How the size of bar is configured? There are some parameters to define to change the size?
Best Regards

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How to disable I/O Bank Source Voltage

July 18, 2017, 7:57 am

≫ Next: Cannot Add new License

≪ Previous: Arria 10 Hard IP Pcie Bar configurations

Hi,
Im working with a D0-Nano Board / Cyclone IV . While i was making some measurement, i conected by a mistake in shortcircuit a GPIO output with 12v from a Voltage Source. That pin was bronken, i couldnt get any signal from it. So i started to find out what to do with this issue.
I ve got about 144 GPIO so having one out of service is not a problem. But after this damage, every time i conect the board to a voltage source, its temperature start to rise high, its sinking a lot of current.
With a multimeter i started to test continuity between GND and the pins, (all pins in normal state are at 3.3v) , and i Checked out that the damaged pin (GPIO_019 - PIND8) is biased to GND, " in short circuit " so that's why mi board is sinking more current than it usually did.
So, something on the chip was broken, so i've been looking for how to disable the block that this pins belong, to avoid this excess of current. But I couldnt find a setting that allows me to do that on Pin Planner.
Every time a conect the board, this one execute the synthesis, the firmware works, but the damaged pins sinks a lot of current so the chips temperature rise very high.

Any idea to solve this?? because at this moment the board is useless.....

best regards.

Links, i Cheked:

https://electronics.stackexchange.co...ations-on-fpga

https://db-electronics.ca/wp-content...7/an-an258.pdf

Cyclone IV Device Handbook, Volume 1, Section II.I/O Interfaces. I/O Banks.

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Cannot Add new License

July 18, 2017, 2:51 pm

≫ Next: banks sharing VCCPD pins

≪ Previous: How to disable I/O Bank Source Voltage

I have a Quartus License that expired over a year ago installed on my computer. We purchased a new license and I am trying to install it. When I go to create a new license for my machine (FPGA-2) I get the following error:

　
A Quartus II SE Fixed already exists on FPGA-2. Only 1 Quartus II SE Fixed can be installed on the same computer.
　
How do I activate my new license?

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banks sharing VCCPD pins

July 18, 2017, 4:14 pm

≫ Next: Importing EDIF To Quartus project

≪ Previous: Cannot Add new License

I am working on a Cyclone V project: part 5CSEBA5U23C8SN

In addition to the HPS "ARM" core I am also creating a NIOS system with its own DRAM, DDR3L, 32 bits wide

I decided to put the DRAM signals on bank 4A. One reason was to facilitate board routing, but the other was because it appeared to be the bank that fit best, getting all the DRAM signals in with minimal left overs. This was imortant as the IO voltage on the bank will need to be 1.35 V and there is no other logic on the board that would interface at this voltage level.

I thought it was a good solution until I discovered that the VCCPD pins are shared between banks 3B and 4A (VCCPD3B4A)

There are 6 of these pins, why couldn't banks 3B and 4A be independent?

Anyway, now I am having difficulty getting enough 3.3V I/O for the other functions due to the limitations of the VCCPD

So I want to make sure I understand this properly.

With any VCCIO voltage 2.5 or less, VDDPD must be 2.5 Volts. Is that correct?

Now comes the really confusing part: With a VDDPD of 2.5 volts, it appears that I can't have a 3.3V LVTTL output, but I can have a 3.3V LVTTL input.
Is that right?

Is there any reason that I wouldn't want to have a 3.3 V signal as an input on bank 3B when VCCPD3b4A is 2.5 Volts?

Thanks

Rod

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Importing EDIF To Quartus project

July 18, 2017, 4:41 pm

≫ Next: VHDL "+" Operator

≪ Previous: banks sharing VCCPD pins

Hello,

I am new to quartus and FPGA implementation. I was given some EDIF files, and want to import them to my project. I was about to go to "Add Files" and point to the EDIF file, but what am I supposed to do next.

The EDIF is of an IP core that has I/O Pins, so I would like to map them in the Pin Planner to the pins I have on my development kit. Please someone guide me how to proceed.

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VHDL "+" Operator

July 18, 2017, 4:59 pm

≫ Next: Quartus II V16: .sdo files not generated

≪ Previous: Importing EDIF To Quartus project

Hello,

I an trying to find and understand how the "+" Operator works in VHDL. I understand the logic and operation of "+" but wanted to know where I can find the library that defines the operator as a function and what kind of binary addition method does "+" make use of as an operator.

Thanks alot in advance :o:o:o

Kind regards,

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Quartus II V16: .sdo files not generated

July 18, 2017, 7:48 pm

≫ Next: Cascaded Interpolation Filter and Restricted Fmax

≪ Previous: VHDL "+" Operator

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