I am new to Quartus software. Is there any possible way to launch the transceiver toolkit GUI using tcl script without using the Quartus GUI? I can only launch the System Console using tcl shell. Or is there any tcl command in System Console for me to launch the transceiver toolkit?
I am using DE0-NANO board for my project and i get the following warning from the pin out voltage. I am using 3.3 V LVTTL for all the pins and 8 mA
I am attaching my pin out file.
Warning (169177): 6 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces.
Info (169178): Pin clk_enable uses I/O standard 3.3-V LVTTL at N9
Info (169178): Pin clk uses I/O standard 3.3-V LVTTL at R8
Info (169178): Pin reset uses I/O standard 3.3-V LVTTL at E1
Info (169178): Pin BCLK uses I/O standard 3.3-V LVTTL at B7
Info (169178): Pin WS uses I/O standard 3.3-V LVTTL at A7
Info (169178): Pin Input uses I/O standard 3.3-V LVTTL at C8
This warning doesn't have any effect on the complitation, i am just concerned if it has any effect on the hardware i am connecting to. The input coming from my external hardware to development board GPIO pins are 3.3 V LVTTL
I would like to implement CNN using OpenCL and run on FPGA.
The CNN implementation will contain 4 kernel function
layer1_kernel, supposed allocate 1 MB local memory
layer2_kernel, supposed allocate 1 MB local memory
layer3_kernel, supposed allocate 1 MB local memory
layer4_kernel, supposed allocate 1 MB local memory
Host program will call clEnqueueNDRangeKernel() function in sequence.
that is, pervious kernel need finished, then the next kernel will be enqueued.
What is the total RAM block resource to be used?
4MB or 1MB?
I'm getting the error that the I_USB_ULPI_CLK port of the "HPS atom" "~GND" needs to be connected to a top-level pin. My problem is ... I can't seem to find this port anywhere in my design to know how to adjust its connectivity. Can anyone tell me what I'm missing?
I'm attaching a picture of the error message, as well as my top-level SOC.v file.
Can someone tell me why I don't have all the usual devices when choosing for the Flash Loader in the "Convert Programming File" window? (See screenshot 1)
If I go in "Add device" in the programmer, you will see that the list is more complete. I specifically need the "EP4CGXCF23", as otherwise it says: (See screenshot 2)
Code:
Error (209025): Can't recognize silicon ID for device 1. A device's silicon ID is different from its JTAG ID.
Most Altera families have register(s) in the I/O cells. Obviously if I want full control of the plumbing I can instantiate the 'GPIO Lite' IP core and do everything explicitly, but I thought that for simple cases the tools would spot a signal coming in on a pin going straight to a register and use the register in the I/O rather than using up an LE.
However, with my current design it isn't doing that - the fitter resource report says "I/O registers 0/863 (0%)", and looking at the Technology Map viewer I can see my signals coming in through an "IO_IBUF" and then getting latched in a LE.
I'm currently working with MAX10 and Quartus Prime 17.0.2 Lite edition (design in VHDL), but I thought I'd seen this working in earlier projects (with Cyclone2/3 and much older versions of Quartus).
Am I missing a setting somewhere, or does this feature not exist?
Hi,
can anyone plz tell me how to remove a program from the EEPROM of the FPGA on the DE0 board (erase the EEPROM content). The EEPROM seems to be not configuring but having stuck with one program causing the FPGA to generate the same output even when different programs are being loaded to it everytime. The EDA tool used is Quartus II v13.1.
Thanks :)
Hi, I'm writing a driver for FreeRTOS+TCP stack. I configured the EMAC1 and DMA peripherals.
At this moment, everything works fine, except that I don't get any interrupt from EMAC1.
So for the moment I poll the EMAC and DMA status bits. I see them come high, and I can clear them by writing 1's.
What I did is :
● Program the GIC to enable interrupt 152 ( ALT_INT_INTERRUPT_EMAC1_IRQ ) ● Set the handler + data ● Set a priority and trigger level ● program the peripheral ( EMAC interrupt mask reg 15, and EMAC/DMA interrupt enable DMA register 7 )
As a test, I tried to get interrupt from UART-0. The device works fine, but I don't see interrupts neither.
The only interrupt that does work is interrupt 29 ( ALT_INT_INTERRUPT_PPI_TIMER_PRIVATE ). That timer is used to get a FreeRTOS system clock.
I downloaded several example designs from altera.com. I have the intelFPGA_pro 17.0 suite installed on my machine.
Compiling and running hello_world and vector_addition was ok.
As I am more interested in doing some HDL library, I tried the fourth example : OpenCL_library (to be found here).
I followed strictly the README.html. Producing double_lib.aoclib went ok. But when I tried to get the .aocx with
, the synthesis failed after some time (approx. 1 hour). I attached the quartus_sh_compile.log as I found some error in it but if you think another log file is worth some attention let me know.
The first error I encountered was:
Code:
Error (13661): VHDL Association List error at i_sfc_logic_c0_entry_test_builtin_c0_enter31.vhd(187): formal "reset_kind" does not exist File: /home_nfs/bourgea/project/xpress_rtl_lib1/library_example1/bin/example1/ip/kernel_system/kernel_system_example1_system/example1_system_140/synth/i_sfc_logic_c0_entry_test_builtin_c0_enter31.vhd Line: 187
The same error is repeated quite some times on other lines and other files. They all concern some
Code:
formal "reset_kind" does not exist
How can I fix this error ?
IMHO, this is not a huge bug but a design example not working out of the box is concerning.
some details about my tools :
Code:
$ aoc --version
Intel(R) FPGA SDK for OpenCL(TM), 64-Bit Offline Compiler
Version 17.0.0 Build 290
I'm trying to build my first DE10 Nano design, and getting some critical fitter warnings that make no sense to me. Specifically, I get the "warning" that, "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details." Then I get the critical warning that, "No exact pin location assignment(s) for 75 pins of 138 total pins. ..." If I look up the "undefined" pins, many of them are HPS_DDR3xxx pins. If I try to assign these pins within the pin editor, I cannot. Instead, they have default locations (matching the schematic) that cannot be changed. There are other warnings as well, indicating that perhaps the DDR3 SDRAM wasn't set up properly, although at this point I have no idea what I might have missed.
I've attached both my top level file, as well as the fit report showing the various I/O errors and warnings I've been receiving.
1) Is there a better way to transfer an array of data from HPS to FPGA and vice versa in Cyclone V Soc (or De1Soc board by Terasic)? I have used PIO and it is more suitable to send one data (or one uint32_t for example) at a time.
2) Is there any component in Qsys that can handle data array? I prefer to use HPS-FPGA bridge rather than Lw_HPGA_FPGA bridge if the data rate is better. I appreciate if some example links are provided.
3) What is the maximum speed of the Lw_HPGA_FPGA bridge can be used?
4) What is the maximum speed of the HPGA_FPGA bridge?
I try to build the opencl code.
The memory blocks in estimated resource usage summary is 35%.
But there is a error message as below:
Error (170048): Selected device has 2713 RAM location(s) of type M20K block. However, the current design needs more than 2713 to successfully fit
How come the memory blocks usage does not exceed 100%, but it still has RAM prolbem related error?
how to avoid the kind of error? any suggestion?
I'm currently designing a Cyclone V DDR3 Ram interface with a single component DDR3L using the hard memory controller. In EMIF handbook I find, that for clock < 933MHz no package deskew is required, I think thats way beyond Cyclone V anyway. However, the emif handbook tells that signals should be routed to be time matched to a maximum skew of 20ps. But when I have a look at the net-length/delay Excel Sheets for the Cyclone V 5CEFA2F23 I find difference in delays for the pads of about 100ps (e.g. DQ0 vs DQ3). So how does it come that I should keep the skew below 20ps when routing while the package itself already has a skew of about 100ps. Doesn't it make sense to account for the package skew even if I'm going to run with about 400MHz clock only? For me it really doesn't cost a lot to account for the package skew as well when routing and I think it will improve the signal quality a lot. Can I use the Excel sheets values for package deskewing or does this break things? Quartus Megawizard doesn't shows me the "Package Deskew Option" for my design, so I get no deskew information from Quartus.
I followed an ethernet tutorial, but there it uses on-chip memory with 2 SGDMA. In this, I think I can send data from Nios to ethernet and ethernet to Nios. But I would like to send the data from FPGA. After reading, I came to know that it can be done if I push the data from FPGA to DDR3 and access DDR3 from NIOS to ethernet and vice versa. But it just theoretical.
I would like to know how can I do it in ALtera tools and is this a right direction to do so?
Hi all,
I read from the Arria 10 Dev Kit User Guide (Page 51 in https://www.altera.com/content/dam/a...FPGA-DK-UG.pdf) that, when plugging the board into a PCIe slot, we should not power supply the board via the 12-V DC jack (J13); instead, it seems that we should be using a 12-V "PCIe 2x4 ATX power connector" for the power supply (J4).
My question is, my PSU only provides two "PCIe 6+2 ATX power connector" for powering PCIe devices; the PSU's 2x4 connector is for motherboard/CPU. I also googled and found that a 2x4 ATX connector is a rarely seen format for PCIe ATX connector. So, is plugging the 6+2 PCIe ATX connector to the Dev Kit OK? The pin patterns (shapes) of the 6+2 connector match perfectly with those of the ATX port on the Dev Kit (which means that I can plug the connector to the port easily without forcing it), and on the 6+2 connector it prints "PCI-E". Based on these observations, my guess was that the 6+2 connector should work; but I also want to make sure doing this won't destroy my board.
Does anyone has any experience on this? Any hint or suggestion is appreciated!
Hi, I created a simple bitstream to blink an LED. It works fine when I download the SOF through JTAG and the LED blinks. But after I programmed the POF to the internal flash, the LED didn't blink after power up. nSTATUS = 2.5V instead of 3.3V(I have 3.3V VCCIO). I tried the latest Quartus 17.0.2, it didn't help. I asked our layout engineer to check the PCB, but he didn't see any problems.
nSTATUS, nCONFIG, and CONF_DONE all have a 10K pullup resistor.
Has anyone seen this problem? Thanks for your comment.
Suppose there are 8 workgroups, each workgroup contains 8 work items.
I declare local memory in kernel function.
__local float A[1000];
if I copy data from global memory, this kind of behavior will increase M20K RAM block usages?
the total M20K is not "local memory size * workgroup number"?
A[1000] * 8