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10G Example design simulation tcl error

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Hi everyone,

I am new to the Altera/Intel framework and maybe some of the questions I am going to ask are really dumb. I am still getting used to the new interface and I don't know where all the options are.

I am trying to create the 10G Example design based on the Low Latency Ethernet 10G MAC IP. The project creation and Analysis & Synthesis work as expected but when I try to simulate the design I am facing some problems with the tool.

As stated in the [Intel Arria 10 Low Latency Ethernet 10G MAC Design Example User Guide], to simulate the design at the command prompt I go to the simulation folder and run the following command.

Code:

vsim -c -do tb_run.tcl
I see the following output of the terminal

Code:

# Top level modules:
#    altera_eth_10g_mac_base_r
# End time: 13:50:11 on Nov 07,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Start time: 13:50:11 on Nov 07,2017
# vlog ./../../../rtl/altera_eth_10g_mac_base_r_wrap.v
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# -- Compiling module altera_eth_10g_mac_base_r_wrap
#

... a lot more of the same, and at the end ...

Code:

# Top level modules:
#    altera_eth_10g_mac_base_r_wrap
# End time: 13:50:11 on Nov 07,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:50:11 on Nov 07,2017
# vlog -sv ./../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_170/sim/altera_xcvr_native_a10_functions_h.sv -work altera_common_sv_packages
# -- Compiling package altera_xcvr_native_a10_functions_h
#
# Top level modules:
#    --none--
# End time: 13:50:11 on Nov 07,2017, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 13:50:11 on Nov 07,2017
# vlog -sv ./../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_170/sim/alt_xcvr_resync.sv -L altera_common_sv_packages -work altera_eth_10gbaser_phy_altera_xcvr_native_a10_170
# -- Compiling module alt_xcvr_resync
# ** Warning: (vlog-2070) Existing protected design unit "alt_xcvr_resync" is being recompiled as unprotected.
# ** Fatal: Unexpected signal: 11.
# ** Error: ./../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_170/sim/alt_xcvr_resync.sv(97): Verilog Compiler exiting
# End time: 13:50:12 on Nov 07,2017, Elapsed time: 0:00:01
# Errors: 2, Warnings: 1
# ** Error: /home/pablo/intelFPGA/17.0/modelsim_ase/linuxaloem/vlog failed.
# Error in macro ./tb_run.tcl line 38
# /home/pablo/intelFPGA/17.0/modelsim_ase/linuxaloem/vlog failed.
#    while executing
# "vlog -sv ./../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_170/sim/alt_xcvr_resync.sv -L altera_common_sv_packages -work altera_eth_10..."
#    ("eval" body line 1)
#    invoked from within
# "eval  vlog -sv $USER_DEFINED_COMPILE_OPTIONS                                    "$QSYS_SIMDIR/../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_na..."
#    ("eval" body line 37)
#    invoked from within
# "com"

As I am using the unmodified generated reference design so I wasn't expecting to face this kind of problems with the simulation.

The error appears to be in this file:

Error: ./../../../rtl/phy/altera_eth_10gbaser_phy/altera_xcvr_native_a10_170/sim/alt_xcvr_resync.sv(97): Verilog Compiler exiting

The content of the file is the following code. The line where the error is pointed is the last endmodule of the code.

Code:

`timescale 1ps/1ps

module alt_xcvr_resync #(
    parameter SYNC_CHAIN_LENGTH = 2,  // Number of flip-flops for retiming. Must be >1
    parameter WIDTH            = 1,  // Number of bits to resync
    parameter SLOW_CLOCK        = 0,  // See description above
    parameter INIT_VALUE        = 0
  ) (
  input  wire              clk,
  input  wire              reset,
  input  wire  [WIDTH-1:0] d,
  output  wire  [WIDTH-1:0] q
  );

localparam  INT_LEN      = (SYNC_CHAIN_LENGTH > 1) ? SYNC_CHAIN_LENGTH : 2;
localparam  [INT_LEN-1:0] L_INIT_VALUE = (INIT_VALUE == 1) ? {INT_LEN{1'b1}} : {INT_LEN{1'b0}};

genvar ig;

// Generate a synchronizer chain for each bit
generate begin
  for(ig=0;ig<WIDTH;ig=ig+1) begin : resync_chains
    wire                d_in;  // Input to sychronization chain.
    (* altera_attribute  = "disable_da_rule=D103" *)
    reg  [INT_LEN-1:0] sync_r = L_INIT_VALUE;

    assign  q[ig]  = sync_r[INT_LEN-1]; // Output signal

    always @(posedge clk or posedge reset)
      if(reset)
        sync_r  <= L_INIT_VALUE;
      else
        sync_r  <= {sync_r[INT_LEN-2:0],d_in};

    // Generate asynchronous capture circuit if specified.
    if(SLOW_CLOCK == 0) begin
      assign  d_in = d[ig];
    end else begin
      wire  d_clk;
      reg  d_r = L_INIT_VALUE[0];
      wire  clr_n;

      assign  d_clk = d[ig];
      assign  d_in  = d_r;
      assign  clr_n = ~q[ig] | d_clk; // Clear when output is logic 1 and input is logic 0

      // Asynchronously latch the input signal.
      always @(posedge d_clk or negedge clr_n)
        if(!clr_n)      d_r <= 1'b0;
        else if(d_clk)  d_r <= 1'b1;
    end // SLOW_CLOCK
  end // for loop
end // generate
endgenerate

endmodule

I am using Ubuntu 16.04 with Quartus II 17.0

Do you have any idea what could cause the problem with the simulation script? I am still learning how to properly use Quartus II and probably someone with more experience can clearly see what the tool is complaining about.

Thanks in advance for your time :)

Linux Boot from QSPI fails

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Hi everyone,

I'm trying to do a system boot from QSPI flash on a custom arria10 board. So far, I have managed to get the fpga image to configure successfully, but am having issues with the Linux side. I am by no means an expert on embedded linux, so if anyone is able to give me any ideas on what is wrong or what I need to fix it would be super helpful. See below for the boot log:

Quote:

[ 0.159880] SMP: Total of 2 processors activated (3188.32 BogoMIPS).
[ 0.159887] CPU: All CPU(s) started in SVC mode.
[ 0.160365] devtmpfs: initialized
[ 0.164547] VFP support v0.3: implementor 41 architecture 3 part 30 variant 4
[ 0.164825] clocksource jiffies: mask: 0xffffffff max_cycles: 0xffffffff, mas
[ 0.166184] NET: Registered protocol family 16
[ 0.166977] DMA: preallocated 256 KiB pool for atomic coherent allocations
[ 0.170893] hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint.
[ 0.170906] hw-breakpoint: maximum watchpoint size is 4 bytes.
[ 0.211931] vgaarb: loaded
[ 0.212238] SCSI subsystem initialized
[ 0.212550] usbcore: registered new interface driver usbfs
[ 0.212619] usbcore: registered new interface driver hub
[ 0.212682] usbcore: registered new device driver usb
[ 0.213056] pps_core: LinuxPPS API ver. 1 registered
[ 0.213064] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giom>
[ 0.213099] PTP clock support registered
[ 0.213283] FPGA manager framework
[ 0.214263] Switched to clocksource timer
[ 0.245038] NET: Registered protocol family 2
[ 0.245640] TCP established hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.245687] TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
[ 0.245752] TCP: Hash tables configured (established 4096 bind 4096)
[ 0.245811] UDP hash table entries: 256 (order: 1, 8192 bytes)
[ 0.245842] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[ 0.246022] NET: Registered protocol family 1
[ 0.246290] RPC: Registered named UNIX socket transport module.
[ 0.246300] RPC: Registered udp transport module.
[ 0.246306] RPC: Registered tcp transport module.
[ 0.246312] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 0.246751] CPU PMU: Failed to parse /sopc@0/pmu0/interrupt-affinity[0]
[ 0.246790] hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 countee
[ 0.247694] futex hash table entries: 512 (order: 3, 32768 bytes)
[ 0.259317] NFS: Registering the id_resolver key type
[ 0.259362] Key type id_resolver registered
[ 0.259369] Key type id_legacy registered
[ 0.259435] ntfs: driver 2.1.32 [Flags: R/W].
[ 0.259752] jffs2: version 2.2. (NAND) �© 2001-2006 Red Hat, Inc.
[ 0.260696] io scheduler noop registered (default)
[ 0.264607] dma-pl330 ffda1000.dma: Loaded driver for PL330 DMAC-341330
[ 0.264626] dma-pl330 ffda1000.dma: DBUFF-512x8bytes Num_Chans-8 Num_Peri-38
[ 0.269216] Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled
[ 0.270514] console [ttyS0] disabled
[ 0.270554] ffc02100.serial: ttyS0 at MMIO 0xffc02100 (irq = 28, base_baud =A
[ 0.834733] console [ttyS0] enabled
[ 0.840026] brd: module loaded
[ 0.843980] cadence-qspi ff809000.flash: Cadence QSPI NOR flash driver
[ 0.851488] CAN device driver interface
[ 0.855949] usbcore: registered new interface driver usb-storage
[ 0.862316] mousedev: PS/2 mouse device common for all mice
[ 0.868236] i2c /dev entries driver
[ 0.872097] watchdog: Invalid min and max timeout values, resetting to 0!
[ 0.879312] Synopsys Designware Multimedia Card Interface Driver
[ 0.885533] ledtrig-cpu: registered to indicate activity on CPUs
[ 0.891713] usbcore: registered new interface driver usbhid
[ 0.897277] usbhid: USB HID core driver
[ 0.901458] fpga_manager fpga0: SoCFPGA Arria10 FPGA Manager registered
[ 0.908682] oprofile: using arm/armv7-ca9
[ 0.913740] NET: Registered protocol family 10
[ 0.919030] sit: IPv6 over IPv4 tunneling driver
[ 0.924290] NET: Registered protocol family 17
[ 0.928747] NET: Registered protocol family 15
[ 0.933178] can: controller area network core (rev 20120528 abi 9)
[ 0.939416] NET: Registered protocol family 29
[ 0.943851] can: raw protocol (rev 20120528)
[ 0.948119] can: broadcast manager protocol (rev 20120528 t)
[ 0.953763] can: netlink gateway (rev 20130117) max_hops=1
[ 0.959459] 8021q: 802.1Q VLAN Support v1.8
[ 0.963683] Key type dns_resolver registered
[ 0.968021] ThumbEE CPU extension supported.
[ 0.972285] Registering SWP/SWPB emulation handler
[ 0.978078] of_cfs_init
[ 0.980583] of_cfs_init: OK
[ 0.985681] ttyS0 - failed to request DMA
[ 0.989833] List of all partitions:
[ 0.993317] 0100 8192 ram0 (driver?)
[ 0.998085] 0101 8192 ram1 (driver?)
[ 1.002691] No filesystem could mount root, tried: jffs2
[ 1.008123] Kernel panic - not syncing: VFS: Unable to mount root fs on unkn)
[ 1.016353] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.1.22-ltsi-altera #1
[ 1.023281] Hardware name: Altera SOCFPGA Arria10
[ 1.027998] [<c0018aa8>] (unwind_backtrace) from [<c0013ad4>] (show_stack+0x)
[ 1.035715] [<c0013ad4>] (show_stack) from [<c059a8a0>] (dump_stack+0x8c/0xa)
[ 1.042911] [<c059a8a0>] (dump_stack) from [<c0598664>] (panic+0xac/0x204)
[ 1.049768] [<c0598664>] (panic) from [<c07b8404>] (mount_block_root+0x254/0)
[ 1.057225] [<c07b8404>] (mount_block_root) from [<c07b861c>] (mount_root+0x)
[ 1.065112] [<c07b861c>] (mount_root) from [<c07b879c>] (prepare_namespace+0)
[ 1.073085] [<c07b879c>] (prepare_namespace) from [<c07b7f1c>] (kernel_init_)
[ 1.081928] [<c07b7f1c>] (kernel_init_freeable) from [<c0597348>] (kernel_in)
[ 1.090075] [<c0597348>] (kernel_init) from [<c000fae8>] (ret_from_fork+0x14)
[ 1.097613] CPU1: stopping
[ 1.100315] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 4.1.22-ltsi-altera #1
[ 1.107242] Hardware name: Altera SOCFPGA Arria10
[ 1.111938] [<c0018aa8>] (unwind_backtrace) from [<c0013ad4>] (show_stack+0x)
[ 1.119653] [<c0013ad4>] (show_stack) from [<c059a8a0>] (dump_stack+0x8c/0xa)
[ 1.126847] [<c059a8a0>] (dump_stack) from [<c001715c>] (handle_IPI+0x294/0x)
[ 1.134215] [<c001715c>] (handle_IPI) from [<c00094b4>] (gic_handle_irq+0x68)
[ 1.141753] [<c00094b4>] (gic_handle_irq) from [<c0014680>] (__irq_svc+0x40/)
[ 1.149200] Exception stack(0xdf507f60 to 0xdf507fa8)
[ 1.154233] 7f60: 00000000 00000000 000002b4 c00227c0 df506000 c082249c 10c00
[ 1.162376] 7f80: c0822450 c05a19c8 00000000 df507fb4 df507fb8 df507fa8 c001c
[ 1.170514] 7fa0: 60000113 ffffffff
[ 1.173992] [<c0014680>] (__irq_svc) from [<c00105dc>] (arch_cpu_idle+0x48/0)
[ 1.181366] [<c00105dc>] (arch_cpu_idle) from [<c005ea38>] (cpu_startup_entr)
[ 1.189599] [<c005ea38>] (cpu_startup_entry) from [<c0016c54>] (secondary_st)
[ 1.198606] [<c0016c54>] (secondary_start_kernel) from [<0000954c>] (0x954c)
[ 1.205629] ---[ end Kernel panic - not syncing: VFS: Unable to mount root f)


I'm using the 16.1 QSPI boot gsrd as reference: https://rocketboards.org/foswiki/Doc...srd161QspiBoot. For the linux side, I am using the precompiled versions of the kernel and root filesystem. I have regenerated a linux dtb based on the sopcinfo of my fpga design. However, I used the gsrd xml files. Those are specific to the devkit, but I figured if something wasn't present in the hardware, it would just be skipped given that there's information about the SD card and NAND flash layout in there. The layout and location of the rootfs are in those xml files and the flash layout I created is identical to the gsrd. The difference is the files inside, so if anyone can point me in the right direction it would be greatly appreciated.

Thanks,
Bogg

Problem with simulation and implementation of code in DE0 Nano Cyclone IV kit

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Hi everyone, I have a kit DE0 Nano Cyclone IV EP4CE22F17C6, it has among other things 8 leds and I am programming in Quartus 12 and for simulate I am using ModelSim Starter 10.0d. My program generates a signal of 8 bits with different patterns. I have done succesfully the Syntensis of my program in Quartus and I created a testbech that generates a signal of 1MHz (that is the only "in signal" that uses my entity) and the simulation works great at the ModelSim. The problem is when I try to test the program in the kit, I use the 8 leds to see the pattern of the 8 bit signal generated and it does not work at all. For testing the code in the kit I created a pll in Quartus that generates a signal of 1MHz, and I ckecked and the pll does generate the signal of 1MHz. What is happening???? In the pictures I post the compilation in quartus and the simulation in ModelSim.
Attached Images

MAX10 PLL External Clock Output

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Hello there,
I'm using the 10M08SCE144A7G FPGA.

In my design I need to give a clk input signal to 3 diferents Analog to Digital Converters. I'm thinking of using a PLL External Clock Output (signal PLL_L_CLKOUTp of the FPGA) to give the clock to these 3 converters.
There is only 1 output of this type with this FPGA.

I'll like to know if there is any recommendations using this output signal to fed 3 diferents Analog to Digital Converters ? (fanout , layout for exemple)
Is this a good way to do it ?

Maybe driving the PLL output to 3 diferents standard fast I/O pins (1 pin for 1 DAC) is a better design ?

Thank you for your help.
Julien.

DE10-Lite not recognized in Quartus Prime 17.02

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I have installed device driver for Altera USB-Blaster. Windows 7 device manager is showing "Altera USB-Blaster" in USB devices but the device is not shown in Tools->Programmer. I have added the device (10M40DCF484) manually using Add Device option. But when I open the SignalTap II Logic Analyzer, I get "No device is selected" in JTAG Chain Configuration. Scan Chain option does not do any action (as seen in the scanned image).
Thank you very much for your help.
Attached Images

A10 HPS boot speed QSPI vs eMMC

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For a typical HPS first, boot from flash boot flow which flash is faster to boot from, QSPI or eMMC? Assumed that all the bloat is trimmed from Angstrom.

QSPI interface is 104 MHz, 4 bit and has no init sequence, I believe. 256 MByte seems to be the biggest available.

eMMC interface is 50 MHz, 8 bit and requires a long init sequence. DDR doesn't seem to be supported. Up to 64 GByte currently available.

Has anybody experience with this?

Is there a difference in power consumption? Any other points to consider when choosing between these two?

Simple MegaCore FFT Simulink Model

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I have build a simple simulink model using MegaCore FFT bolck. I gave the following inputs to the fft megacore block.


Code:

      reset_n      : 1
      inverse      : 0
      sink_valid  : 1
      sink_sop    : counter counts 0 to 127, if count ==0 then sink_sop =1
      sink_eop    : counter counts 0 to 127, if count ==127 then sink_eop =1
      sink_real    : unsigned 8 bit value
      sink_imag    : unsigned 8 bit value (0)
      sink_error  : 2 bit (00) no error
      source_ready : 1


unfortunately no output.....:cry: What is the mistake I have done?


here is the simulink model.


Waveform input according to the above mentioned order


Simulink mdl file also attached with the post.
Attached Images
Attached Files

interfacing to epcq from fpga?

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Hello all,

I've been assigned a task at work that requires me to access the epcq from the fpga in order to store data on it. However, the epcq is used for storing the configuration file for the fpga and it is hardwired to dedicated programming pins which are impossible to access through the fpga fabric. is it possible to access epcq in this configuration through the use of one of the flash ip modules?

thanks for any help that can be provided!

Error! Sorry. An error occurred when creating your account. Please try again.

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I tried to create an account several times in the past month but I always get this message when submitting the registration form:

"Error! Sorry. An error occurred when creating your account. Please try again. "

Linux SD Card Boot Error: Failed to start Connection Service

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Hi,

I'm using a Cyclone V SoC FPGA Development Kit and am booting Linux from an SD card. I am following instructions from Rocket Boards Cyclone V SoC development guide here https://rocketboards.org/foswiki/Doc...velopmentBoard.

However when I launch Minicom and warm reset the board, everything is [OK] apart from one thing towards the end of the boot, which reads:

[FAILED] Failed to start connection service.
See 'systemctl status connman.service' for details. I have attached screenshot.

I read it may be due to faulty SD card. If anyone has ran into this problem before, any support would be appreciated!

Thanks
:confused:
Attached Images

Quartus II Pro BluePrint can not launch

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So, here's the condition I got.
I was using QuartusII Pro 16.1 to build up my design, which including EMIF controller of DDR4 and using 10AX066 as core FPGA. So far it ran well, I can do most of the functions that tool supports including BluePrint.
However, after a 30 days trial, I'm using the purchased license but the problem occurs. When I trying to launch BluePrint and select "YES" in the pop-up dialog, the Quartus II is closed and meanwhile, the other start image appeared but after that, the BluePrint simply hanging and having no response. In the task manager, I can see a "quartus_pdp" appeared in task list but no further actions.
In the forum, I saw similar issues below:
1. https://www.alteraforum.com/forum/sh...ight=Blueprint
2. https://www.alteraforum.com/forum/sh...ight=Blueprint

However, both of the discussion threads point to license issue, but I don't know what specific steps I should do. The purchased license I'm using is a floating one and it's the first time I'm using BluePrint to arrange pin placement.

Any idea? thanks!!!

hdmi cyclone 2...

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Hi I'm new here.

I've recently bought a cheap cyclone 2 dev board, EP2C5T144 with the soul intent can I produce a picture via HDMI (DVI) expressed from the IO pins of the fpga directly, looking around I found some nice information from fpga4fun, however some of the code is for xilinx based chips such as the dcm. Long story short I've set her up and getting no output, I wonder what gives?

I've added a ALT_PLL, started with 50mhz in and output 25mhz and 250mhz clocks , after which followed the brief explanation of hdmi on a fpga at fpga4fun as best I can, the only thing cyclone 2 didn't support but cyclone 3 does support is the alt_buf's so I used assigns and directly apply the changes that way to the output tmds[x] p/n and pixelclock. Still nothing.

pulled my hair out for a few days over this, I wonder if anyone else has been successful.

One guy has ... https://github.com/charcole/NeoGeoHDMI the question is why doesn't his code work for me (stripped it down to the parts I require) if anyone has a similar setup or the same board, could they walk me through what I'm meant to do exactly, I've followed the pin sheet on his wires.md specifically to the hdmi cable and breakout board options I have and no signal, the only thing that gets a result is the 5v line but that's it 'hdmi is available' no signal.

Writing this project in verilog and would appreciate some help. To start with a low compatible resolution and test pattern would be sufficient first step.




Chris

Quartus does not create .sdo file

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Hello everyone,

The problem is clear. I am able to make functional simulation but not same for timing simulation. I attached the error ss. Most of developers had said that Quartus creates the file while it is compiling but it did not do it.

Thanks.
Attached Images

run time error in altera FOGA

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we are using altera FPGA with TI transmitter board. after some time quartus gives error. The snapshot of error is attached.
and some time in windows a message prompt that one of your USB is malfunctioning.
Attached Files

Stuck on Fast QSPI

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I have a 100 MHz clock generated by an internal PLL in a Cyclone IV design, and I would like to read from a QSPI peripheral at 100MHz (i.e. 400Mbit per second).

That seems like it should be possible, and I have had some success on prototype hardware. I wrote logic that is pulling data from flash at 100 MHz on real hardware without data errors. However, it fails timing in Quartus. I do not expect it to work reliably over process/voltage/temperature variations.

I would like to correct the design so that it passes timing, but I am stuck because I have not worked with a serial interface this fast before. Usually I am dividing down from a master clock (e.g. 100 MHz -> 25 MHz). I have PLL outputs available for phase shifting, but I do not know how to apply or constraint them. I have not been able to find any examples of this situation.

Can anyone help or point me to any resources on this scenario? I have not been able to find anyone locally who knows enough about timing constraints.

how to simulate NIOS II generated in Qsys_Pro v17.0

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Hi,

I'm using Quartu_Prim_Pro v17.0, I use QsysPro to generate a NIOS II system and testbench, when I try to run simulation using cadence NCSIM, I found the NIOS cpu model is encrypted and not able to generate any waveform on NIOS core output ports.

I was using Quartus II v13.1, the NIOS simulation model did not have such problem.

Did I miss anything?

Any comment is welcome.

Thanks.

GPIO programming in firmware

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Hi,
I have 3 gpio pins in HPS which I have to program via firmware(HPS shared IO's) which will decide my further sequence. I am booting my system through SD card.

What is the sequence of programming the GPIO? eg. like resetting the bridge(H2F) and then programming gpio or programming gpio first and then resetting bridges?
At what point in firmware should I program these GPIO's(immediately after core.rbf loads or at some later instant of time)?

How to create a device tree for a custom arria 10 board?

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Hi,
has anyone expirence wirh creating a Linux device tree (using sopc2dts) for a custom arria 10 board?
The default approach for a development board is:
$ sopc2dts --input ghrd_10as066n2/ghrd_10as066n2.sopcinfo --output ghrd_10as066n2.dts --board hps_a10_common_board_info.xml --board hps_
a10_devkit_board_info.xml --board ghrd_10as066n2_board_info.xml --bridge-removal all --clocks
But on a custom board i don't have the two xm files. Do i have to geneate the dts without those XML files and then edit everything additional needed by Hand?

how to map many ports to a vector/array ?

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Hi All,

I have an entiry with a lot of ports. I'd like to map these ports to a vector/array.

Example:
Ports:
bit_000_0 : in std_logic;
bit_000_1 : in std_logic;
bit_000_2 : in std_logic;
bit_000_3 : in std_logic;
bit_000_4 : in std_logic;

Desired mapping of the ports to a vector:
vec (0) <= bit_000_0;
vec (1) <= bit_000_1;
vec (2) <= bit_000_2;
vec (3) <= bit_000_3;
vec (4) <= bit_000_4;

Can I use a function/package for this purpose? There are a lot of such ports (~150), so I'd like to do these assignments in the separate file (e.g. package) and do not clutter the top entity/module file. Is this possible?

Thank you!

Problem with aocl install

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Hi,
I have a problem with the installation command "aocl install<path_custom_platform>", because the bash returns the following problem:
"is not an object at /home/intel_tools/intelFPGA_pro/17.1/hld/share/lib/perl/acl/Command.pm line 1290, <F> line 34." I am using a virtual machine with centOS 7.4 on Windows server 2012 R2. I attached the screenshot of the problem. Can anyone help me? Thanks for your help.
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