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Write/Read RAM memory from FPGA.

November 11, 2017, 6:16 pm
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Hello. I'm using de0-nano-SoC kit for some experiments. I'v already figure out how to access to the RAM memory from HPS side, I can read or write data there (trough /dev/mem). So I don't have problems with Linux/"C" part.

The next step is writing/read data from FPGA. I use DE0_NANO_SOC_GHRD as base project. It has "incip_memory2" added in Qsys, so I didn't make any changes there. Then I'v added "RAM: 1-PORT" symbol to the project ( https://screencast.com/t/6GT4CtTy ).
What I have to do now, to access this Symbol on my "GHRD" base project? As I understand i have to write code in ghrd.v but I don't know how))
Please, provide small peace of code where I can assign first byte of RAM to 0x1 for example, or redirect me to some tutorial, where I can understand clearly how to implement symbols (such as "RAM: 1-PORT") in the code.
Many thanks! :)
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I have a problem with .elf files.

November 12, 2017, 12:25 am
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Hello guys, I have a problem about missing .elf file when I'm using complie in monitor program.

I've read some posts in this forum and I included all files in same folder. And then, I tried to remove this problem.

Although I included all files in a folder, I got this error again

nios2-elf-objcopy -O srec "C:/sample_de1_soc/Lab7/part1/part1.elf" "C:/sample_de1_soc/Lab7/part1/part1.srec"
C:\intelFPGA\16.1\nios2eds\bin\gnu\H-x86_64-mingw32\bin\nios2-elf-objcopy.exe: 'C:/sample_de1_soc/Lab7/part1/part1.elf': No such file


I don't have any idea about this error. I need your help
It occurs again and again.
Attached Images
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Why is my inout signal converted to output by eda netlist writer?

November 12, 2017, 4:02 am
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My simple test dut consists of the following code. When I run a compile on this code (Processing ->start Compilation) the netlist written by the EDA Netlist Writer has signal defined as output instead of inout. I am unable to figure out what I am doing wrong. Any hints or help in identifying the issue is welcome.

Code:
module test(                                                   
        input dir,
        inout signal,       
        input clk,
        input rst_n
);                                             
reg intreg;
always @(posedge clk or negedge rst_n)begin
        if (~rst_n)
                intreg<=1'b0;                                       
        else begin
                if (dir)
                        intreg<=signal;

        end 
end       
assign signal=dir?1'bz:intreg;
endmodule
The generated netlist is

Code:
// Device: Altera 10M08SCE144C8G Package EQFP144
//

//
// This Verilog file should be used for ModelSim-Altera (Verilog) only
//                                             

`timescale 1 ps/ 1 ps
       
module test ( 
        dir,
        signal,
        clk,           
        rst_n);
input  dir;
output  signal;
input  clk;
input  rst_n;

the .v and .vo files are attached for reference.
Attached Files
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Fitter Error with LOANER option on cyclone V

November 12, 2017, 6:28 pm
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HI

I'm working with LOANER option for can communicate the HPS UARTbut when i compile the system generated by qsys i have errors in the fitter part. The error is the next:


Error (179000): Design requires 206 user-specified I/O pins -- too many to fit in the 145 user I/O pin locations available in the selected device
Info (179001): Current design requires 206 user-specified I/O pins -- 206 normal user-specified I/O pins and 0 programming pins that have been constrained to use dual-purpose I/O pin locations
Info (179002): Targeted device has 145 I/O pin locations available for user I/O -- 117 general-purpose I/O pins and 28 dual-purpose I/O pins




i'm following the instructions from Altera's LOANER Manual and i ran the TCL scrip but this not work. I dont know why if i'm using the generated archive


Somebody can help me please? I'm ussing a DE10 Nano by Terasic.
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MMC failing on linux-altera on CycloneV/Atlas-SoC, while ltsi kernel is not

November 11, 2017, 7:53 am
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I'm setting up a Linux system on a CycloneV on Atlas-SoC, and I'm using Yocto Pyro to build. I'm using meta-altera from https://github.com/kraj/meta-altera to build the kernel. The preloader and u-boot is built using Quartus 17.1 and EDS. I'm using meta-linaro and use Linaro GCC 6.3.

If I select KERNEL_PROVIDER="linux-altera-ltsi" which is now at 4.1.33, everything boots fine. However if I select KERNEL_PROVIDER="linux-altera" and version 4.12 or 4.11, I get failures in MMC, which ultimately fails the boot.

Any ideas to why?


Code:
    [    1.625114] mmc_host mmc0: Bus speed (slot 0) = 200000000Hz (slot req 25000000Hz, actual 25000000HZ div = 4)
    [    1.634925] mmc0: new SD card at address 9a6c
    [    1.639825] mmcblk0: mmc0:9a6c SU02G 1.84 GiB
    [    1.651203]  mmcblk0: p1 p2 p3
    [    1.788574] mmcblk0: error -110 transferring data, sector 136328, nr 264, cmd response 0x900, card status 0x0
    [    1.828493] mmc_host mmc0: Bus speed (slot 0) = 200000000Hz (slot req 400000Hz, actual 400000HZ div = 250)
    [    1.925149] mmc_host mmc0: Bus speed (slot 0) = 200000000Hz (slot req 25000000Hz, actual 25000000HZ div = 4)
    [    2.138569] mmcblk0: error -110 transferring data, sector 136328, nr 264, cmd response 0x900, card status 0x0
    [    2.148602] mmcblk0: retrying using single block read
    [    2.268567] mmcblk0: error -110 transferring data, sector 136337, nr 255, cmd response 0x900, card status 0x0
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Quartus programmer software for 32-bit PC

November 13, 2017, 12:34 am
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Hello,

Where can I get Quartus II software version 14.02 32-bit installer?

Reimo
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Blank "License Setup Required" page for Quartus 17.0 on Centos 7.4.1708

November 13, 2017, 1:24 am
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Hi,

We are trying to install Quartus 17.0 on an ovh instance running Centos 7.4.1708.
After installation when we invoke <installdir>/quartus/bin/quartus, we get a black screen with heading "License Setup Required" (screen-shot is attached).
We were expecting this screen to give us text-boxes where we could provide our license files.
Can someone give a clue as to what are we missing here.

Thanks,
reniac
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Iterations executed serially across the regions listed below.

November 13, 2017, 1:56 am
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================================================== ==
|-+ Loop "Block43" (file conv.cl line 162)
| Pipelined with successive iterations launched every cycle.
|
| Iterations executed serially across the regions listed below.
| Only a single loop iteration will execute inside the listed regions.
| This will cause performance degradation unless the regions are pipelined well
| (can process an iteration every cycle).
|
| Loop "Block44" (file conv.cl line 163)
| due to:
| Memory dependency on Load Operation from: (file conv.cl line 188)
| Store Operation (file conv.cl line 190)
| Store Operation (file conv.cl line 190)
| Load Operation (file conv.cl line 205)
|
| Loop "Block44" (file conv.cl line 163)
| due to:
| Memory dependency on Store Operation from: (file conv.cl line 190)
| Store Operation (file conv.cl line 190)
|
|
|-+ Loop "Block44" (file conv.cl line 163)
| Pipelined with successive iterations launched every 2 cycles due to:
|
| Pipeline structure: every terminating loop with subloops has iterations launched at least 2 cycles apart.
| Having successive iterations launched every two cycles should still lead to good performance
| if the inner loops are pipelined well and have sufficiently high number of iterations.
================================================== =========================
In the optimization report, there are some parts like this which say my blocks will be executed serially (For example block 44). And I assume it means there's no pipelining. But the report also says the block44 will be launched every 2 clock cycles. What does this mean?

Any advice would be greatly appreciated!!
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OPAE technology

November 13, 2017, 2:17 am
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Hi everyone,
I have a problem for using OPAE Intel open source technology. I'm not able to set the environment varìable MTI_HOME. I don't know the path to set. Can anyone help me?
Thanks for your help.
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Problem in NiosII based design with different instructions and data memories

November 13, 2017, 2:33 am
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Hello,

I am a beginner in using qsys for systems design. I have made a simple design that contains:
- niosII processor ("e" version)
- on chip memory for instructions connected to the niosII instruction_master port
- on chip memory for data connected to the niosII data_master port
- jtag UART connected to the niosII data_master port

Then, I have made a simple project "Hello world" using the the "Nios II software build tool".

The problem is when I ran this project, I do not get the message "Hello from NiosII" on the "niosII Console". However, when I use the same on chip memory for data and instructions (connected to data master port and instruction master port at the same time), I get the message.
So, would you please, explain to me why my design does not work with two on chip memories (one for data and one for instructions) and how can I fix this?

I am working with Quartus prime 17.0 on Attila Arria 10 board.

Thanks.
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Cyclone V, sharing memory between FPGA and HPS

November 13, 2017, 4:21 am
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Hello. I'm using de0-nano-SoC and want FPGA and HPS to have access to the same memory. I use GHRD as base project. In Qsys I have activated "enable in-system memory content editor" to see how it works. When system is started I can see TWO Instances, and it's strange, because I have only one on_chipmemory2_0 in Qsys.
In the following code in Verilog I write some bytes to RAM:
Code:
soc_system_onchip_memory2_0 m(.address(0)
, .byteenable(4'b1111)
, .chipselect(1)
, .clk(FPGA_CLK1_50)
, .clken(1'b1)
, .reset(hps_fpga_reset_n)
, .reset_req(1'b0)
, .write(1'b1)
, .writedata(32'hF0F0F0F0)
, .readdata(datain)
);

As result I can see these bytes in in-system memory editor : https://screencast.com/t/yOkuCoK2pKxj but I can find it only in the second Instance (see screenshot)

On my C part I use the following code to get base address:
Code:
#define HW_REGS_BASE ( ALT_STM_OFST )#define HW_REGS_SPAN ( 0x04000000 )
#define HW_REGS_MASK ( HW_REGS_SPAN - 1 )
#define ALT_AXI_FPGASLVS_OFST (0xC0000000) // axi_master

virtual_base = mmap( NULL, HW_REGS_SPAN, ( PROT_READ | PROT_WRITE ), MAP_SHARED, fd, ALT_AXI_FPGASLVS_OFST );
Then, when I use C app to change memory on this base address I can see these changes in in-system memory editor: https://screencast.com/t/5W9LjT1jjtP

So, I can't interact between FPGA and HPS because FPGA uses "second" instance and HPS uses "first" instance of "on_chipmemory2_0"(??).

Can you please explain why I have two Instances on in-system memory editor and how I can get "first" instance form FPGA, or "second" instance from HPS to be able share data between them.

Many thanks! I'm golang developer and new in FPGA, will appreciate if you help!
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Cannot obtain IP address of SoC Cyclone V using SD image from OpenCL SDK 17.1

November 13, 2017, 9:03 am
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Hello,

I am trying to establish connection between host and board via ethernet but I cannot obtain IP address of the SoC Cyclone V board. I am using the latest SD image from Intel FPGA OpenCL SDK 17.1 .I've also managed to compile and run some design examples using OpenCL. When it's booting the image I get this error message:

Sending discover...
libphy: stmmac-0:04 - Link is Up - 1000/Full
Sending discover...
Sending discover...
No lease, failing

Also on the LCD it shows: '"No IP obtained Hello Tim"

I've also tried GSRD 17.1 image from rocketboards.org and I can obtain IP address successfully. However, I need OpenCL compatible SD image. Are there any quick fixes or I'll need to install OpenCL on GSRD 17.1 image?
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License of Quartus Prime Pro

November 13, 2017, 9:54 am
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Hi everyone,
I would like to say how to configure correctly the license for Quartus Prime Pro, because of I'm using a virtual machine with centOS v7.4 (the host system is Windows Server 2012 R2). I generated the license with the physical address of the host system, but Quartus is installed in the VM.
Can anyone help me? Thanks for your help.
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Cyclone V won't configure via active serial

November 13, 2017, 2:14 pm
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I have a Cyclone V design (5CSEBA5) that I am trying to configure using a EPCQ128 device

I have created a .sof file that I can load into the FPGA directly (Jtag USB Blaster) and it works fine (blinks my user debug LED)

I have tried to take that same .sof file and create the file to program the EPCQ128, but I am not sure I am going about this the right way.

I used the "Convert programming file" program with the following settings

Programming File Type = Jtag Indirect Configuration file
Configuration device = EPCQ128
Mode = Active Serial x 4
File name = output_fille.jic
create memory file and create config data boxes are NOT checked
under "input files to convert" there are:

Flash Loader
5CEBA5
SOF Data
romulus.sof


The romulus.sof file is the same one that I can load directly and get my blinking LED

I generate the file, then use the stand alone programmer. I autodetect the FPGA, then "attach" the EPCQ128

In the box for assigning the files I select the EPCQ128 and "change" the file (I discovered that you MUST change the file, not "add"!) to point to the jic file just created.

I check the box for programming the EPCQ128 and click start. The FPGA programs with the "factory default SLF" image and the it erases and programs the EPCQ128.

I can verify the EPQC128, so everything looks okay.

But then I power cycle and expect the FPGA to configure from the flash device, but it fails.

I have the MSEL[4:0] pins set to 10011 (standard active serial). I have also tried 10010, for FAST AS.

I can probe the pins on the EPCQ128 and I see:

DCLK is going at about 80 MHz.
nCSO is mostly low, with a short pulse high every 175ms
The four data pins are toggling

The nCE pin to the FPGA is tied low
NCONFIG and NSTATUS are pulled high (10K) - (addition: Nstatus does get asserted low every 175 ms)
Config_done drives a FET which in turn drives an LED. This circuit works as expected when I program the FPGA directly via JTAG


I figure that the basic JTAG connection to the FPGA is okay as I can configure it directly and it appears I can program the FLASH device through it.

The connections between the FPGA and serial FLASH device appears to be proper because I can program and verify the FLASH

I am suspecting that I didn't create the .jic file properly but I don't know what to do different.

I am using a .jic file because that is the only format that the programmer will allow me to select for the file that will get programmed into the attached flash device.

I would really appreciate any help here!

Rod
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Avalon to AXI bridge for Nios II in Qsys

November 13, 2017, 3:20 pm
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Hello,
I am trying to build a simple Qsys SoC consisting of a Nios II/e with on-chip memory. I also require to translate the Nios II signals from Avalon to AXI. Is there any IP in Qsys which does this? On exporting the Nios II signals to AXI, these AXI signals would be used with a megawizard-created DDR3 controller.
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Cyclone V Hard Memory Controller MPFE bandwidth

November 13, 2017, 4:45 pm
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I have a QSYS design which uses DDR memory. The DDR memory is clocked at 400Mhz in the Hard Memory Controller, and is 32 bits wide, so max bandwidth (not allowing any latency!) is 2*400,000,000*32 = 25.6Gbps.
I then connect the Multi-Port Front-End (MPFE) controller of the HMC up by setting 2 ports, both 128 bits wide, bidirectional. There are clocked at 168MHz, so theoretical bandwidth on each of these is 128bits * 168MHz = 21.5Gbps.

I now have some VIP suite Frame Buffers hooked up and I run into bandwidth problems. I start with 1 frame buffer enabled, processing 1080p60 video, which is 1920x1080x20 (bits per pixel) x 60 (frames per second) = 2.5Gbps. The Frame buffer has a read and a write port, so we actually need 5Gbps. Running 1 frame buffer at 1080p60 is fine. If I enable a second one though, they both struggle for bandwidth (it seems) as the video breaks up. Given that we're at 2/5 bandwidth of the DDR memory itself, and around 1/2 bandwidth of one AVL interface to the MPFE we should be fine. I have another design that this works fine with, but I cannot get it to work in this one.

If anyone could check my bandwidth calcs, and/or explain why I would be limited in my bandwidth then I'd greatly appreciate it.

Cheers,
Simon
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Cannot find example pipemultQP16_1 timing 2.zip ?

November 13, 2017, 5:46 pm
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I am looking for beginner examples files for Quartus II tutorial but am unable to find them.
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Read and print data from local memory .

November 13, 2017, 5:49 pm
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Read and print from local memory .
Please, Do you can tell me if we can read and print the data stored in local memory. My data is defined as __local adress space in the kernel and setKernelArg in host code will be NULL. Also, As I understood, no buffer should be created with function Clcreatebuffer for local memory . So after, that When I try to read and print data in this local memory I have a huge and random number like this 343467048 , 7984984 . My output number should be 0 to 10 as I store it in local memory. But I call printf function to see my output in local buffer and I has 30984984..
So, Should I create buffer for local address space with Clcreatebuffer ?
How I can read my output stored in local memory ?
Where this huge and random number come ?
My code :
Kernel is :
__global uint *restrict X
__local uint * Z)
Z[index]=X[index];
Host :
input_X_buf[i] = clCreateBuffer(context, CL_MEM_READ_ONLY, n_per_device[i] * sizeof(cl_uint), NULL, &status);
status = clEnqueueWriteBuffer(queue[i], input_X_buf[i], CL_TRUE,0, n_per_device[i] * sizeof(cl_uint), input_X[i], 0, NULL, &write_event);
status = clSetKernelArg(kernel[i], argi++, sizeof(cl_mem), &input_X_buf[i]);
status = clSetKernelArg(kernel[i], argi++, sizeof(cl_mem), NULL);
status = clEnqueueReadBuffer(queue[i], output_Z_buf[i], CL_FALSE,0, n_per_device[i] * sizeof(cl_uint), output_Z[i], 1, &kernel_event[i], &finish_event[i]);
printf(" Device %d, index %d output_Z: %d ref_output: %u ",i, j, output_Z[i][j], ref_output[i][j]);
Thanks in advance for your help.
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how to design Filters using verilog and nios? like butterworth, high and low pass etc

November 13, 2017, 10:06 pm
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Dear sir,
I am Mtech final year student. Right now I am working on ac energy parameter monitoring system. In my project I want to design filters for noise reduction like low pass , high pass , butterwort, chebysev etc... so can u plz suggest me how to make filter in fpga using Verilog. Step for implementing , any notes, materials etc....
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Intel HLS Compiler (aka i++) Error:No definition found for speed grade '-7' Cyclone10

November 13, 2017, 11:21 pm
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Hi guys, I've installed Intel HLS Compiler (aka i++) together with Intel® Quartus® Prime Pro Edition 17.1 to try it out. After setup, I can run the test in "HLS Getting Started Guide" document successfully, which proves the i++ compiler works.

But, when I switched to my own C source file, i++ threw an Error as follows:
$ i++ mips.c -march=10CX220YU484I6G -o test-fpga
Error: No definition found for speed grade '-7' in family 'Cyclone 10 GX'.HLS Verilog code generation, llc FAILED.

I have picked up the device 10CX220YU484I6G because my Quartus license only support Cyclone 10 family and I need a big device from this family.
Is this error caused by that i++ cannot support a specific speed grade in this family?
If so, which devices in this family are supported by i++? Or, where can I find the document that lists the devices supported by i++ (I didn't find this info from the Intel HLS documents)?

PS: my OS info,
OS: Ubuntu 14.04.3 LTS
gcc/g++ versions: both 4.4.7

Thanks in advance for any possible suggestions and help:)
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