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Qsys Error: Failed to elaborate classic module C:/Users/.../yysystem.ptf

December 14, 2017, 5:37 am
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Hello,
i didn't touch my project for a while.
Now i get the error:
Error: Failed to elaborate classic module C:/Users/.../AppData/Local/Temp/alt7407_3755802541581721576.dir/0007_sopclgen/yysystem.ptf (254)

In other topics they told to close qsys, quartus and reboot the system but that all didn't help.

I only changed some c and h files on my NIOSII code (nothing related to the qsys)
Is maybe the quartus installation corrupt? If maybe yes, how to reinstall it preferably (install over the old, remove reinstall)?

Quartus II 64Bit 12.1 SP1 installed

Below the last messages of th Generate log before the error occurs:

Code:
Info: Starting classic module elaboration.
      1 [main] sh (6408)  C:\altera\12.1sp1\quartus\bin\cygwin\bin\sh.exe: *** fatal error -  cygheap base mismatch detected - 0xE708D0/0x612708D0.
This problem is probably due to using incompatible versions of the cygwin DLL.
Search for cygwin1.dll using the Windows Start->Find/Search facility
and delete all but the most recent version.  The most recent version *should*
reside in x:\cygwin\bin, where 'x' is the drive on which you have
installed the cygwin distribution.  Rebooting is also suggested if you
are unable to find another cygwin DLL.
      0 [main] sh 5140 fork: child -1 - forked process 6408 died unexpectedly, retry 0, exit code -1073741819, errno 11
C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh: fork: retry: Resource temporarily unavailable
      2 [main] sh (6756)  C:\altera\12.1sp1\quartus\bin\cygwin\bin\sh.exe: *** fatal error -  cygheap base mismatch detected - 0xE708D0/0x612708D0.
This problem is probably due to using incompatible versions of the cygwin DLL.
Search for cygwin1.dll using the Windows Start->Find/Search facility
and delete all but the most recent version.  The most recent version *should*
reside in x:\cygwin\bin, where 'x' is the drive on which you have
installed the cygwin distribution.  Rebooting is also suggested if you
are unable to find another cygwin DLL.
1090043 [main] sh 5140 fork: child -1 - forked process 6756 died unexpectedly, retry 0, exit code -1073741819, errno 11
C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh: fork: retry: Resource temporarily unavailable
      1 [main] sh (1376)  C:\altera\12.1sp1\quartus\bin\cygwin\bin\sh.exe: *** fatal error -  cygheap base mismatch detected - 0xE708D0/0x612708D0.
This problem is probably due to using incompatible versions of the cygwin DLL.
Search for cygwin1.dll using the Windows Start->Find/Search facility
and delete all but the most recent version.  The most recent version *should*
reside in x:\cygwin\bin, where 'x' is the drive on which you have
installed the cygwin distribution.  Rebooting is also suggested if you
are unable to find another cygwin DLL.
3170757 [main] sh 5140 fork: child -1 - forked process 1376 died unexpectedly, retry 0, exit code -1073741819, errno 11
C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh: fork: retry: Resource temporarily unavailable
      2 [main] sh (3976)  C:\altera\12.1sp1\quartus\bin\cygwin\bin\sh.exe: *** fatal error -  cygheap base mismatch detected - 0xE708D0/0x612708D0.
This problem is probably due to using incompatible versions of the cygwin DLL.
Search for cygwin1.dll using the Windows Start->Find/Search facility
and delete all but the most recent version.  The most recent version *should*
reside in x:\cygwin\bin, where 'x' is the drive on which you have
installed the cygwin distribution.  Rebooting is also suggested if you
are unable to find another cygwin DLL.
7258297 [main] sh 5140 fork: child -1 - forked process 3976 died unexpectedly, retry 0, exit code -1073741819, errno 11
C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh: fork: retry: Resource temporarily unavailable
      3 [main] sh (776) C:\altera\12.1sp1\quartus\bin\cygwin\bin\sh.exe:  *** fatal error - cygheap base mismatch detected - 0xE708D0/0x612708D0.
This problem is probably due to using incompatible versions of the cygwin DLL.
Search for cygwin1.dll using the Windows Start->Find/Search facility
and delete all but the most recent version.  The most recent version *should*
reside in x:\cygwin\bin, where 'x' is the drive on which you have
installed the cygwin distribution.  Rebooting is also suggested if you
are unable to find another cygwin DLL.
15338349 [main] sh 5140 fork: child -1 - forked process 776 died unexpectedly, retry 0, exit code -1073741819, errno 11
C:/altera/12.1sp1/quartus/sopc_builder/bin/nios_sh: fork: Resource temporarily unavailable
Error: Failed to elaborate classic module  C:/Users/ith/AppData/Local/Temp/alt7407_3755802541581721576.dir/0022_sopclgen/yysystem.ptf  (254)
Info: Finished elaborating classic module.
Now i found out that after a certain version checked in in svn the QSYS doesn't work any more. So i made a diff of the two versions, see pictures:





But there are only .c, .h files and .cproject and Makefile which are different, and all in the "..\software\ALD02070_socket" and not in the "..\software\ALD02070_socket_bsp" folder!
In my opignion, to generate the QSYS i don't need any files in the software folder or are i'm wrong?
First i need to generate the QSYS, then generate the bsp, and then compile the software. So i think that the QSYS is not dependent of all in the software\...socket folder...

Sorry, the picture SVN_Folders.gif is automatically reduced to a very low quality even it is only 50kB...
So i try to load it in two separate pics..
Attached Images
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Driving DCLK pin after FPGA configuration

December 14, 2017, 5:58 am
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Hi,

We are using 10CL016 FPGA and configuring it in Passive serial mode from a Host processor. The SPI clock is connected to the DCLK pin of FPGA.

We need to use the Host SPI interface even after configuration is done. We see that as per datasheet DCLK pin can't be used as I/O after configuration in passive serial mode. Hence, we have connected the same clock to one more adjacent I/O pin. This will enable us to use the SPI interface after configuration through this I/O, however after configuration DCLK pin will also be driven at the same time.

Is it fine to drive the DCLK pin even after configuration is over? Will it create any issues?

Regards
Raja
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Which licenses do I have checked out?

December 14, 2017, 6:37 am
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Hi there,

My company has a pool of licenses that I can check out. However, my workplace (research center) is remote and the connection does not always work. The company is willing to obtain more licenses but I need to know which ones specifically we need.

This is for a complex project (medical imaging), and such there is a lot of IP in the project that I have not touched.

Thanks,

Tom
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Driver problem

December 14, 2017, 7:36 am
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Hi,
I've got some driver problems:
I'm using Quartus II 64-bit v13.1 and a DE0-nano board.
I know it DID work for a last year project but now (after having compiled another project with no error) my programmer can't find any hardware. What could I do?
Thanks.
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Adding ethernet capability to a Nallatech 395 FPGA card

December 14, 2017, 8:21 am
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Hi,

This might be a stupid question, but I need some help. I have a Nallatech 395 FPGA card that I want to connect to an ethernet hub. The card has SFP+ ports (not familiar with them, unfortunately) and want to connect it to my network so that I can send data back and forth through the network. What do I need to do to get that running? Here is the card:

Thanks,

QG

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Wherer does Quartus put files?

December 14, 2017, 8:53 am
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I seem to be playing whack-a-mole With Quartus.
I make a change and when I compile, Quartus will undo my change and find the error.
I even did a search on the folder and found another .vhd file with the same name and changed it also.
After compiling, it still will undo the change and give the same error.
Please help.
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HPS SPI slave

December 14, 2017, 9:26 am
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In my HPS system I have enabled the SPI Slave 0 (SPIS0 is set to FPGA, and Mode is set to Full).

In my device tree source (in the XML file) I have:
Code:
<DTAppend name="spi@0xffe02000" type="node" parentlabel="sopc0" newlabel="hps_0_spis0"/>
<DTAppend name="compatible" type="string" parentlabel="hps_0_spis0" val="snps,dw-spi-mmio-15.1" />
<DTAppend name="compatible" type="string" parentlabel="hps_0_spis0" val="snps,dw-spi-mmio" action="add" />
<DTAppend name="compatible" type="string" parentlabel="hps_0_spis0" val="snps,dw-apb-ssi" action="add" />
<DTAppend name="interrupt-parent" type="phandle" parentlabel="hps_0_spis0" val="hps_0_arm_gic_0" />
<DTAppend name="interrupts" parentlabel="hps_0_spis0">
        <val type="number">0</val>
        <val type="number">156</val>
        <val type="number">4</val>
</DTAppend>
<DTAppend name="#address-cells" type="number" parentlabel="hps_0_spis0" val="1"/>
<DTAppend name="#size-cells" type="number" parentlabel="hps_0_spis0" val="0"/>
<DTAppend name="reg" parentlabel="hps_0_spis0" >
    <val type="hex">0xffe02000</val>
        <val type="hex">0x1000</val>
</DTAppend>
<DTAppend name="spi-max-frequency" parentlabel="hps_0_spis0" >
    <val type="number">100000000</val>
</DTAppend>
<DTAppend name="enable-dma" parentlabel="hps_0_spis0" >
    <val type="number">1</val>
</DTAppend>
This gets compiled into a device tree blob and loaded onto the system. When it boots, I get the error:
"Trying to free already-free IRQ 188" (this is 156+32 so is the SPI IRQ number).
And loading the driver then bombs out.
If I comment out the interrupt lines then it instead complains about lack of interrupt resource.

What am I doing wrong? Why can't I get the SPI driver to load?

Cheers,
Simon
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IOPLL Source Synchronous Compensation Issue? -- Arria 10

December 14, 2017, 11:02 am
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I have a design using a source synchronous input and I am generating the latch clock from an IOPLL in source synchronous compensation mode. The description of that mode states:
"If you select the source synchronous mode, the clock delay from pin to I/O input register matches the data delay from pin to I/O input register."

Based on that, I'd expect the latch clock delay to be close to the data path delay. Unfortunately, TimeQuest does not show this. It shows the full data delay, with the latch clock edge occurring at the PLL phase offset value.

The input device is an ADC w/ edge-aligned, double data rate, outputs. All of the inputs are LVDS.
  • The ADC output clock is 250 MHz (4000 ps period).
  • The data skew values relative to the DCO are: min: -160 ps, max: +360 ps.
  • The IOPLL is setup in source sync compensation mode to generate a 250 MHz clock w/ a +90 degree (1000 ps) phase shift.
  • The data lines from the FPGA pins go to IBUFs and then to DDIO_IN registers that are clocked by the PLL output signal.
  • Using Quartus Pro 17.0.2, build 297
  • I've read app note AN-433 (May-2016), and "Source Synchronous Timing" by Ryan Scoville.


This is an edge-aligned, double data rate source synchronous case w/ the PLL using a +90 degree phase shift.

When analyzed, the data arrival path shows a typical result of an IOB delay(500 ps), and the data delay from the IOB to the register(850 ps). So the overall data delay is 1710 ps from launch clock to data arrival.
The data required path shows the IBUF delay, routing delays to the PLL, and a number of internal PLL delays. It also shows a compensation block that compensates for the majority of the delays in the PLL. This results in the latch clock arriving at 1000 ps - the PLL phase shift amount.

The source synchronous compensation behavior of the PLL: "clock delay from pin to I/O input register matches the data delay from pin to I/O input register" does not seem to be evident. It looks like it is running in "normal" compensation mode, where the PLL compensates for the delay of the internal clock network used by the clock output.

All of the IBUFs, and DDIO_IN registers are in the IOBs (typically col X148 in this part: Arria10 10AS066N3F40E2SG)
Constraints:
  • 250 MHz virtual clock for the ADC
  • 250 MHz clock for the ADC DCO clock input pins
  • Calls to derive_pll_clocks and derive_clock_uncertainty after the clock creation lines
  • Min and max input delay constraints on the input data lines for the rising and falling edges referenced to the virtual ADC clock.
  • False paths for the setup fall_to/rise_from the virtual and fall_from/rise_to the PLL output clock
  • False paths for the hold fall_from/rise_to the virtual and rise_from/fall_to the PLL output clock


Questions:

  1. Why does the source synchronous compensation mode not seem to do what it states? (why does it appear that the data delay from pin to register is not compensated for by the clock?)
  2. Why does the data path delay increase proportionally when I adjust the PLL phase shift value to account for the negative slack in the original design?
  3. Am I misunderstanding something regarding the PLL, source sync compensation, etc?
  4. Am I missing something in the constraints, etc. that is preventing this from working?


Thanks,

--Mike V.
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Quartus Pro v16.1 Design Partitions Window missing 'Preservation Level' functionality

December 14, 2017, 11:14 am
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Hi

I am working on a large FPGA design, and the Quartus Pro's Incremental Block-Based Compilation Feature would be very useful to me. I am currently following a tutorial on Incremental Block-Based Compilation : Design Partitions lecture from Altera's website (https://www.altera.com/customertrain...ion_html5.html) . My Quartus software (i.e. Quartus Prime Pro version 16.1) has a design partitions window but i can't find the important 'Preservation Level' functionality as described by the tutorial.


Please does someone know why this is so? and where i can find this important functionality in order to perform incremental compilation on my research project?
(i attached the Design Partitions Window)

Thanks
W
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NIOS can not boot from EPCS ?!!!

December 14, 2017, 1:03 pm
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Hi guys , im trying to make the NIOS II boot from the same EPCS where the configuration is stored.
Im using Quartus 13 and it has only the legacy serial flash controller. The documentation says the first 1-Kbyte of the address space of the flash controller is a ROM bootloader . So I set the value of the reset vector to the address of the serial flash controller , and the reset offset to 0x00000000 (pointing to the bootloader) and the exception vector pointing to On-chip RAM . I then converted the .SOF of the FPGA and the .elf file of the NIOS app to flash files using the following commands:
sof2flash --input=hw.sof --output=hw.flash --epcs --verbose
elf2flash --input=sw.elf --output=sw.flash --epcs --after=hw.flash –verbose
nios2-elf-objcopy --input-target srec --output-target ihex sw.flash sw.hex
then I followed the following method to program the EPCS using Altera USB blaster: 1. Open the Convert Programming File tool from the file menu in Quartus II
2. Select .jic file for “Programming file type”
3. Select EPCQ256 for “Configuration device”
4. Make sure “Active Serial” is selected for “Configuring device mode”.
5. Click on “Flash Loader”, then click on “Add Device” to select the Cyclone V device you’re using then click “Ok”.
6. Click on “SOF Data”, then click on “Add File” to select the .sof file generated by Quartus II compilation.
7. Click on the .sof file you have just added, click on “Properties” and enable the “Compression”
Page 3 of 4
8. Click the “Add Hex Data” button
9. Select “Relative Addressing”
10. Select your <project>.hex file containing your Nios II software image
11. Click on “Generate” to generate the .jic file
I then re-power , the FPGA configuration works , but the NIOS is not booting as it should (Whole design working on 25 MHz)
Now whats the problem ?
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Weird messages when compiling for emulation

December 14, 2017, 3:53 pm
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I've been using the tools for a while now and just came across a strange message while compiling for emulation.

"Scalarizer can't handle insertelement with non-constant index: %vecins = insertelement <16 x float>%31, float %.099, i32 %mul19, ! dbg !338"

and many more lines just like that.


Strangely the compiler does finish and prints "Emulation compilation completed successfully". I'm still trying to track down what's causing this, but this is the first time I've tried compiling for emulation using the float16 data type. It may also be just a bad line of code somewhere.

Has anyone seen this behavior or know what it means? I'm unsure if the compiler succeeded or not...

UPDATE: I've found the lines of code and they were simple writes to the float16 variable with the index equal to twice the for loop index variable. I've been able to replace them and removed the weird messages; however the question remains.
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Cyclone 10 GX EMIF PLL clock input

December 14, 2017, 7:29 pm
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After compiling a EMIF for Cyclone 10 GX, I noticed that it insists on using an external differential clock. Attempts at routing internal PLL output to pll_ref_clk input results in error. Does that mean I have to use an external LVDS oscillator, or loop a differential PLL output back to this?
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Print TDO on JTAG Chain Debugger

December 15, 2017, 2:01 am
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Hello,

I have a JTAG chain of 3 devices; I used JTAG Chain Debugger to go through the JTAG chain step-by-step.

In the example that I attached, I sent an IR instruction to bypass the first 2 devices, and select the ID register of Device 3 (UNKNOWN_1000143). Then, I shift the data registers and I get the correct ID (1000143) for device 3.
What I want to do is use a .svf to automate the previous commands; I saved the session log and I get the following content for the .svf:
Code:
ENDIR IDLE;
ENDDR IDLE;
SIR 18 TDI (3FFF1); !TDO (15511)
SDR 34 TDI (000000000); !TDO (001000143)
I also tried to move the semicolon and remove the "!" which I guess is for comments, but I have the same result: "Success to execute file...".
Code:
ENDIR IDLE;
ENDDR IDLE;
SIR 18 TDI (3FFF1) TDO (15511);
SDR 34 TDI (000000000) TDO (001000143);
I even tried to play with MASK and SMASK (I am still confused with their differences).

Is it possible to print the value of TDO with JTAG Chain Debugger; or is it something the tool does internally during step-by-step operations?


Thanks,

Damien
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pcie/altera_xcvr_native_a10_171/sim/mentor/twentynm_pcs.sv segfault?

December 15, 2017, 8:43 am
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Code:
Start time: 17:39:56 on Dec 15,2017vlog pcie/altera_xcvr_native_a10_171/sim/mentor/twentynm_pcs.sv
Model Technology ModelSim - Intel FPGA Edition vlog 10.5c Compiler 2017.01 Jan 23 2017
** Fatal: Unexpected signal: 11.
** Error: pcie/altera_xcvr_native_a10_171/sim/mentor/twentynm_pcs.sv(12): in protected region
End time: 17:39:56 on Dec 15,2017, Elapsed time: 0:00:00
Did anybody experience this with modelsim ase in 17.1?
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Basic Audio Output on DE2 audio codec

December 15, 2017, 3:55 pm
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Hello,

I am a beginner to FPGAs and VHDL. I am really interested in learning more about the audio codec ( WM8731/WM8731L Wolfson ) on my DE2 board but I find that there is either a lack of information about this or, the examples that I find are too overwhelming for me. I want to start with sending audio, Can someone show me a super simple example of how audio is sent to the line-out port on Codec? Or guide me in the right direction?

This is what I think I know so far; There are a couple of pins that I need to use, an DAC Left Right audio pin, output pin, and maybe a clock. I also think the correct respective pins would be: AUD_DACLRCK ( Pin C6 ), AUD_DACDAT ( Pin A4 ), and AUD_XCK ( Pin A5 ).

Once I specify those pins I will use as ports, I need to create a 24 Bit string that I'll use as the "output signal". I'll assign this string to the left right audio pin. Then i dont know what id do after. does this sound like a good approach so far?
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Custom QSYS component do not instantiate generic parameter correctly.

December 16, 2017, 1:22 am
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Hello
I created a custom qsys component with generic parameters (baud rate of a UART for example).

If I add my component to a NIOS configuration I can change the parameters of my component properly.

The changed properties are however not reflected in the generated qsys vhdl code. In the VHLD configuration the parameters keep their default values.

After some analysis I see that the parameter property in the tcl file "HDL_PARAMETER" is missing in the TCL file.

Manually adding this property to the tcl seems to solve the problem.

My question: How can I set the HDL_PARAMETER in the component wizzard ? What did I do wrong, is this a bug ?

Best Regards,
Johi.
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TimeQuest command precedence for clock group

December 16, 2017, 7:02 am
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Hi Forum.

In my system I got several clock domains and it is quite handy to set clock groups instead of false commands on thousands of paths. However it is not clear what happens to those ip fifo automatically generated sdc commands for crossing clock domains such as max delay or max skew. If they are then ignored then set clock groups is misleading and useless in my system.

Any thoughts especially from Timequest gurus. Thanks in advance.
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Quartus 17.1 SegFaults on Compilation Start - HELP?

December 16, 2017, 10:18 am
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Hi - so in order to upgrade to 17.1, I bought a new PC (my old one was running Centos 5), and I installed Centos 17.3 (current release). I downloaded and installed Quartus 17.1.

When I start compilation, it pauses for about 5 sec, and then it crashes with a Segfault (see below). It's not 100% consistent. The first time I tried loading some projects built in 17.0 it ran, once (re-run caused SegFault), and if I created a new project it SegFaulted 1/2 the time on the first run (and 100% on subsequent runs).

Sometimes I just get the message

Segmentation Fault quartus (core dumped).

Sometimes I get something like

kang2/jwinston67:
*** Fatal Error: Unhandled exception
0x8171: ERR_STACKWALKER::get_stack_trace(void const**, int, int, void*) + 0xb1 (ccl_err)
0xb015: err_terminator() + 0x4b (ccl_err)
0x63796: __cxxabiv1::__terminate(void (*)()) + 0x6 (stdc++.so.6)

0x63a36: __cxa_rethrow + 0x46 (stdc++.so.6)
0x1a5b64: QEventLoop::exec(QFlags<QEventLoop::ProcessEventsF lag>) + 0x2f4 (QtCore.so.4)
0x1aa7c4: QCoreApplication::exec() + 0xb4 (QtCore.so.4)
0x1ea8: qgq_main(int, char const**) + 0x68 (quartus)
0x40720: msg_main_thread(void*) + 0x10 (ccl_msg)
0x602c: thr_final_wrapper + 0xc (ccl_thr)
0x407df: msg_thread_wrapper(void* (*)(void*), void*) + 0x62 (ccl_msg)
0xa559: mem_thread_wrapper(void* (*)(void*), void*) + 0x99 (ccl_mem)
0x8f92: err_thread_wrapper(void* (*)(void*), void*) + 0x27 (ccl_err)
0x63f2: thr_thread_wrapper + 0x15 (ccl_thr)
0x427e2: msg_exe_main(int, char const**, int (*)(int, char const**)) + 0xa3 (ccl_msg)
0x1f7a: main + 0x26 (quartus)
0x21c05: __libc_start_main + 0xf5 (c.so.6)

HELP???
/j
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HPS2FPGA bridge, DMA

December 16, 2017, 5:17 pm
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Hello everybody, i'm trying to make some simple project on DE1-SoC and have problems with H2F bridge. I have a GHRD as a base and i try to read from Onchip RAM to HPS RAM. Problem is that i don't really sure that i work with OCRAM. I can write and read from 0xc0000000+, but when i initialize OCRAM with .hex file in QSYS and then read this data from bare-metal app, i read nulls. Looks like i read from other undefined place.

I initialize bridges like that it was in my university labs:

Code:
if (status == ALT_E_SUCCESS)    {
        status = socfpga_bridge_setup(ALT_BRIDGE_LWH2F);
    }


    if (status == ALT_E_SUCCESS)
    {
        status = socfpga_bridge_setup(ALT_BRIDGE_H2F);
    }
Code:
ALT_STATUS_CODE socfpga_bridge_setup(ALT_BRIDGE_t bridge){
    printf("INFO: Setup Bridge [%d] ...\n", (int)bridge);


    ALT_STATUS_CODE status = ALT_E_SUCCESS;


    if (status == ALT_E_SUCCESS)
    {
        // STEP 12:
        status = alt_bridge_init(bridge, NULL, NULL);//  Attempt to initialize the bridges
    }


    if (status == ALT_E_SUCCESS)
    {
        status = alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM,
                                      ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM,
                                      ALT_ADDR_SPACE_H2F_ACCESSIBLE,
                                      ALT_ADDR_SPACE_LWH2F_ACCESSIBLE);
    }


    if (status == ALT_E_SUCCESS)
    {
        printf("INFO: Setup of Bridge [%d] successful.\n\n", (int)bridge);
    }
    else
    {
        printf("ERROR: Setup of Bridge [%d] return non-SUCCESS %d.\n\n", (int)bridge, (int)status);
    }


    return status;
}
I dont know should it work with initialized in qsys ocram, or if i dont want to fill ocram myself, i need to something else?

I read try to read like that:
Code:
for (uint32_t i = 0; i < 128; ++i)    {
        printf("FPGA_RAM= [%x]\n",(unsigned int)alt_read_word(ALT_H2F_BASE+ALT_H2F_RAM_OFFSET+offset));
        temp++;
        offset=offset+4;
    }
where ALT_H2F_BASE=0xc0000000, and ALT_H2F_RAM_OFFSET=0x00000000.

And the second question for my future plan is how to make dma transfer fron fpga ram ro hps ocram? is there enough alt_dma_memory_to_memory() or i should do this another way?

I've never worked with SoC and it difficult for me to understand some things and Altera manuals.



P.S.: sorry for mistakes i'm bad in english, but i hope you understand and will help me. Thanks:rolleyes:
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can single work items kernels run in parallel on same device

December 16, 2017, 7:04 pm
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Can single work item kernels run in parallel on the same device (i.e. on the same board).

I've been trying to get a very simple example of task parallelism working but have not been able to
to get more than one kernel to run at the same time on the same board.

The kernel computes part of summing equations - let's say it sums numbers from "start" to "end".
In a .cl file there are multiple identical kernels that do this - let's say there at 12 of them.

Single work items kernels have been used to insure that the equation can be pipelined.

The host code creates multiple kernels and multiple contexts in an effort to run more than one in parallel.
After trying many, many things, I've yet to get them to run in parallel. Initially I used just the time profile
to see how much time they take to run. Each kernel takes about the same time (e.g. 25 ms). If 12 kernels
are started, the time is 300 ms.

There are four identical boards in the system. If 12 kernels are used and three are used on each of the four
boards then each one takes 25 ms but each board can run them in parallel so the total time is only 75 ms.

What else is needed to get the kernels to run in parallel on the same board. I've been able to turn on
profiling and can see that each one is started - one after the other.

Everything seems to work (i.e. the correct answer is produced) but the kernels don't run at the same time on
a single board.

Do I need to use NDR range kernels?

Any suggestion would be greatly appreciated! (this should be so hard?!?)
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