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[QSF] how to use variables + how to include another script?

January 5, 2018, 7:49 am
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Hi All,

1) How can I use the local/environment variables inside of the QSF file?

Howsome the regular TCL variable assignment does not work for me:
%> set a "AAA";

2) How to use the SOURCE_TCL_SCRIPT_FILE in the following command? How should it work?
%> set_global_assignment -name SOURCE_TCL_SCRIPT_FILE "<path>/vars.tcl"

3) inside of the QSF I've put the following line:
source <path>/<filename.tcl>

The <path> is an absolute path to the file and the file is physically exists in its location, but Quartus Prime issues an error message that it cannot find the file.... Why? How to fix?

Thank you!
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Download Files button on Altera website

January 5, 2018, 9:33 am
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Hello,

On dl.altera.com, hitting the Download Files Button produces this error:


This site can’t be reached
wwwqa.altera.com’s server IP address could not be found.

DNS_PROBE_FINISHED_NXDOMAIN

Happens with any browser, any computer, either at work or at home.

Does anybody recognize this ?

Thanks
Gary
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Compile error 169025 Too many I/O pins assigned in I/O bank

January 5, 2018, 10:17 am
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My design is based on a FPGA online course I'm taking through Coursesea
I'm seeing a conflict between the compile error and the pin planner
I'm using Quartus 16.1 lite (free), processor MAX10 10M08DAF484C8GES
I did research the forum for help, no luck. I'm also the Max10 datasheets
Compile error states 37 pins assigned in I/O bank 8 only 36 I/O pins allowed
versus
Pin planner shows 33 pins assigned and 3 pins available, see IO Bank Usage attachment

Per the instructor direction I assigned the pins from a combination of
- pin planner:
  • 2 single pins dropped
  • dropping grouped bus pins into the bank #

- using the pin Assignment Edito:
  • other single pins.


OMG I just discovered copying / pasting the compile error below I get the signals i placed in bank 8 plus there's 3 ~signals that I didn't place but this only adds up to 36 pins not 37.
- So what is the 37th pin?
- why did these signals get placed? One confession I did do a back annotate before re-assigning the pins.
Info (169112): Pin ~ALTERA_CONFIG_SEL~ Info (169112): Pin ~ALTERA_nCONFIG~
Info (169112): Pin ~ALTERA_nSTATUS~

Error (169025): Too many I/O pins (37) assigned in I/O bank 8 - no more than 36 I/O pins are allowed in the I/O bank
Info (169112): Pin A[31]
Info (169112): Pin A[30]
Info (169112): Pin A[28]
Info (169112): Pin A[26]
Info (169112): Pin A[24]
Info (169112): Pin A[22]
Info (169112): Pin A[20]
Info (169112): Pin A[18]
Info (169112): Pin A[16]
Info (169112): Pin A[14]
Info (169112): Pin A[12]
Info (169112): Pin A[10]
Info (169112): Pin A[8]
Info (169112): Pin A[6]
Info (169112): Pin A[4]
Info (169112): Pin A[2]
Info (169112): Pin A[0]
Info (169112): Pin A[1]
Info (169112): Pin A[3]
Info (169112): Pin A[5]
Info (169112): Pin A[7]
Info (169112): Pin A[9]
Info (169112): Pin A[11]
Info (169112): Pin A[13]
Info (169112): Pin A[15]
Info (169112): Pin A[17]
Info (169112): Pin A[19]
Info (169112): Pin A[21]
Info (169112): Pin A[23]
Info (169112): Pin A[25]
Info (169112): Pin A[27]
Info (169112): Pin A[29]
Info (169112): Pin reset_n
Info (169112): Pin ~ALTERA_CONFIG_SEL~
Info (169112): Pin ~ALTERA_nCONFIG~
Info (169112): Pin ~ALTERA_nSTATUS~
Attached Images
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[SDC] Input/Output delay for All ports -> script writing

January 5, 2018, 10:49 am
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Hi All,

How can I create the timing constraints (set_input/output_delay) for all ports (excepting clocks and reset ports)?

Let's say the design has the following clocks: clk0, clk1, clk2 and following resets: rstn0, rstn1, rstn2 and hundreds of other ports.

How can I write a script, which set input delays of 0ns for all input ports (excepting clk0, clk1, clk2, rstn0, rstn1, rstn2) and output delays of 0ns for all output ports?

Thank you!
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SD Card on DE0

January 5, 2018, 11:33 am
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Does anyone know how to dump program to SD Card on DE0 Board?
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[Quartus] init file -> how to source an additional file -> where located?

January 5, 2018, 12:13 pm
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Hi All,

I'd like Quartus will run some tcl file each time it starts (no matter what project will be open after that).

How can I do so?

Thank you!
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Intel HLS compiler GCC Error

January 5, 2018, 2:06 pm
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Hi,

I'm trying to get the examples for the intel HLS compiler to work (included with Quartus Prime 17.1). As per the initialization requirements, I run:

source init_hls.sh

I then get an error regarding vsim not being on the path. No problem, I run the following command:

export PATH=$PATH:/opt/intelFPGA/17.1/modelsim_ase/bin

and try again:

source init_hls.sh

I now and able to use i++! So, to compile the example, I run:

make test-gpp

and that works. Creates an executable, and runs with "Success" as the output.

Now the real test:

make test-x86-64

and poor alas, it fails. Error:

i++ counter.cpp -march=x86-64 -o test-x86-64
In file included from counter.cpp:1:
In file included from /opt/intelFPGA/17.1/hls/include/HLS/hls.h:11:
/opt/intelFPGA/17.1/hls/include/HLS/hls_internal.h:5:10: fatal error: 'queue' file
not found
#include <queue>
^
1 error generated.
HLS x86-64 compile FAILED.
make: *** [Makefile:40: test-x86-64] Error 1

This is likely an issue related to GCC. <queue> is a part of the standard GCC library, but why does it not find it when using the i++ command?
I've tried a plethora of things to get this to work, including using the 'include' directive in the makefile to where queue is found. This leads to deeper and deeper problems.
I've also tried pointing to the GCC libraries included in the modelsim directory. Same problems as using the system GCC libraries and header files.

Any thoughts on where I'm going wrong?

--I'm using Fedora 26 64bit.
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Arria 10 SoC Development Kit - Access all pins via on board Max 5 FPGA

January 5, 2018, 2:36 pm
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Hi,
I am using Arria 10 SoC Development Kit (10AS066N3F40E2SG).
There are few addotional fpgas on the board (Max5). Seems like these FPGAs works as a multiplexer to deliver signals from the periphery to the main FPGA(Arria10) and back as the Arria10 has not enough pins to access all the periphery instantly.
There is a diagram that show how some of the periphery connected to the FPGA via Max5 (push buttons, leds, etc. - attached screen shot).
But there are many signals that are going from the periphery to max5 without any explanation how to access them from the main FPGA.
There are also many signlas going from the FPGA to max5, but again there is no any diagram with explanation how these signals are connected further/ between them.
There are all the talkabout pins in the schematics of the board (page 35 : 5M2210 System Controller and page 36 - FPGAIO for DP_IOSDI_IO and FMC_3V3IO) rev.c.
Of course, I can try to reprogram max5 as I want, but I dont think this is the way Altera design it..
Did someone faced that issue, and found how to access the all the periphery?

Thanks in advance.
Attached Images
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Intel HLS compiler issue

January 5, 2018, 4:48 pm
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Hi,

I've been using the Intel HLS compiler for a bit now and have gone ahead and started using the tool beyond the examples provided, but I ran into an issue. Typically the software (x86) and the verilog match up. However in this instance I got a discrepancy. At first I thought it was due to using random to generate values, but as I don't change the seed the pattern should be the same across runs. Here's a small snippet:

int main(){
int ret;
bool same;
for(i=0;i<100;i++){
data = rand() % 10;
ret = comp_func(data, &same);
printf("ret : %d same?: %s\n",ret,(same)?"yes":"no");
...
}
...
}

Is this okay that there exist discrepancies between the two versions?

Thanks,
Elias
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Cyclone V SFP

January 4, 2018, 5:05 am
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I have designed Cyclone V transceiver board, by connecting directly from Cyclone V FPGA to SFP.

I have tried many ways to transmit and receive from SFP. But i can't receive the data.

May i know the steps to implement the SFP with Cyclone V.

Also let me know, if any other IP need to implement SFP using Cyclone V.
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Efficiency improvements after switching to 17.1 from 17.0

January 4, 2018, 7:22 am
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Just as an FYI: I noticed significant resource savings on the same code when switching to version 17,1 of the tool from version 17.0. I'm not sure if this is common for new releases of this tool but thought I should mention it. If you're getting tight on resources it may be worthwhile to install 17.1 alongside whatever version you're using and try it out. (Note: don't forget to use a BSP that supports 17.1).
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BareMetal vs MPL (Minimum Pre-Loader)

January 4, 2018, 9:52 am
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Hello all,

After several days of research here on the forum, the wiki, rocketboards, and google, I'm stumped as to which way to go with a new Cyclone V SOC (dual core) project.

My requirement is simple - don't use Linux as the OS but use another OS instead - looking at mAbassi which seems to be a great solution for using both C5 cores with SMP (symmetrical multiprocessing).

Would appreciate arguments for/against using MPL, as well as helpful hints on how to use the SPL but insert mAbassi (or any other non-Linux OS).

thanks.
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Cyclone 10 LP - PLL reconfiguration example design

January 4, 2018, 10:37 am
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I have been following AN661 and how to video: https://www.altera.com/content/dam/a...h-mif-file.mp4 to understand how the PLL reconfiguration can be implemented. i am targeting Cyclone 10 LP - 10CL025 part and using Quartus Prime Lite 17.1 tools. i know that the application note and video are targetting older parts, i was told by the support person to use these as reference to target this new FPGA. 'ALTPLL' and 'ALTPLL_RECONFIG' IPs i see in the tool show different inputs enabled when selecting the reconfiguration option in the PLL wizard than it is shown in the video and AN661.

Attached 'allpll.jpg' and 'pll_reconfig.jpg' are what i see in the tool. But the above video (snippet attached 'video_setup.jpg' ) show different inputs enabled for PLL and pll_reconfig for PLL reconfiguration application.

Questions:
- How do I get to ‘Altera IOPLL’ IP option as shown in the video for cyclone 10LP part ?
- Enabling the dynamic reconfiguration, gives me the scanxxx signals? How do I get to the IP configuration as shown in the video and AN661 example designs?
- Is there any tutorial or app note with step by step instructions for PLL reconfiguration for Cyclone 10LP part?

Thank you very much!
Attached Images
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DE1 Board unable to "auto detect" (no hardware)

January 4, 2018, 2:28 pm
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Hello to everyone,

I've been using the DE1-cycloneV for two years at university. I bought one for me now but there is something which worries me: the board makes constant noises i didn't hear before. For example, at the startup flashing routine it periodically makes these noises whenever 7-segments/leds blink.

Anyone has an idea on what could it be? Thanks.
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emulator some times give different output

January 4, 2018, 11:23 pm
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quartus compile error Case choice must be a locally static expression

January 5, 2018, 12:14 am
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Hi,

i compile a code in quartus that has case-when statements nested in a for loop and each value checked depends on the loop variable.
Quartus complains on this with the error 'Case choice must be a locally static expression'.

Is there any workaround for this problem? it would be manually hard to unroll the loops.
I tried to change vhdl version to 2008 but did not help. I also saw some discussion on setting a parameter --relax <someting>...

For the record, this case-when statements did not produce an error when compiling on Sinplify

Thanks
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[TCL] query_collection -> why not working?

January 5, 2018, 4:36 am
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Hi All,

I'm working on the following example:
https://www.altera.com/support/suppo...tual_pins.html

Here is the script:
Code:
load_package flow
proc make_all_pins_virtual {} {    execute_module -tool map    set name_ids [get_names -filter * -node_type pin]    foreach_in_collection name_id $name_ids {        set pin_name [get_name_info -info full_path $name_id]        post_message "Making VIRTUAL_PIN assignment to $pin_name"        set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON    }    export_assignments }
The script itself works without problems.

But, when I try to list as the contents of the created collection using the query_collection command, I receive the following error message:
> query_collection
Error:ERROR: Quartus Prime Tcl command "query_collection" is only available for use in the following executables:
Error: quartus_fit
Error: quartus_sta
Error: while executing
Error:"query_collection _collection0"


Why? What's the problem? How can I list the created collection of the pins?

Thank you!
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Odd behavior with matching-case (vhdl 2008)

January 5, 2018, 6:43 am
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Hello!
I'm trying to use the matching-case syntax introduced in vhdl 2008 but I'm having a bit of a problem. Take the following piece of code, say a register map for example:
Code:
      clk  : in  std_logic;
      rst  : in  std_logic;
      addr : in  std_logic_vector(7 downto 0);
      reg0 : out std_logic;
      reg1 : out std_logic;
      reg2 : out std_logic;
      reg3 : out std_logic

....

  process (rst, clk)
  begin
      if (rst = '1') then
        reg0          <= '0';
        reg1          <= '0';
        reg2          <= '0';
        reg3          <= '0';
      elsif (rising_edge(clk)) then
        reg0          <= '0';
        reg1          <= '0';
        reg2          <= '0';
        reg3          <= '0';
        case? addr is
            when x"00" =>
              reg0    <= '1';
            when x"1-" =>
              if (addr(3 downto 0) = "0011") then
                  reg1 <= '1';
              else
                  reg2 <= '1';
              end if;
            when others =>
              reg3    <= '1';
        end case?;
      end if;
  end process;
The second when in the case above is where I'm having trouble. The compiler will set reg1 to always '0' (which you can check in the RTL viewer). This sort of makes sense to me because since you told the compiler you didn't care about the first 4 bits it just assumed the if would fail and reg1 is hardwired to '0'. However, I'm not entirely convinced this assumption is correct, what I would expect is to always fall into this specific case regardless of the lower 4bits but sill use their actual value inside. For example, if you changed it to
Code:
when x"1-" =>
    dataout <= addr(3 downto 0)
wouldn't you expect the output to be the same as the 4 lower bits of the address input? Compiling this gives you a dataout stuck at GND (as notified by a warning message or seen in the RTL viewer).

Thank you all for your help!
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[TCL] basic commands -> why not working?

January 5, 2018, 7:34 am
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Hi All,

1) How should the regular TCL commands work in the Quartus Prime Console?

Somehow the following very basic commands do not work for me:
%> ls
%> dir
%> echo "..."

2) Is there a command, which clears the Quartus Prime Console display from the previous commands (like 'clear' in linux)?

Thank you!
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[QSF] how to use variables + how to include another script?

January 5, 2018, 7:49 am
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Hi All,

1) How can I use the local/environment variables inside of the QSF file?

Howsome the regular TCL variable assignment does not work for me:
%> set a "AAA";

2) How to use the SOURCE_TCL_SCRIPT_FILE in the following command? How should it work?
%> set_global_assignment -name SOURCE_TCL_SCRIPT_FILE "<path>/vars.tcl"

3) inside of the QSF I've put the following line:
source <path>/<filename.tcl>

The <path> is an absolute path to the file and the file is physically exists in its location, but Quartus Prime issues an error message that it cannot find the file.... Why? How to fix?

Thank you!
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