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Qsys error:While creating NEW IP

March 13, 2018, 2:27 am
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Hi , I am trying to create a new component on Qsys using my verilog code in quartus. I am getting some errors [please look over the attachment], I don`t know how to fix it. Please guide me

Verilog code
Code:
module coun    (
 LED    ,  // Output of the counter
 clk    ,  // clock Input
 );
 input clk;
 output reg LED;
 reg [31:0] out=0; 
always @(posedge clk) begin
 out <= out + 1;
 LED=out[29];
end
endmodule
I need step-step training please
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Multiple CPLD's + JTAG's question

March 13, 2018, 6:10 am
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Good morning,

This my first time working on CPLD's, so I apologize for my mistakes.

I am working on a design that would include 3 CPLD's (5M1270ZT144I5N). All were receiving 64 signals, some controls, and delivering 8 outputs. At first, all were going to be identical, so after some research, I decided to go with a single JTAG connection for all of them.

However, as it turned out in the rest of the circuit, I would just need 8 outputs out of all three (instead of 24). I have been playing with the design to have the 3rd CPLD receiving the outputs of the other 2 as inputs, and then 8 outputs for the rest of the circuit. Now that I would need 2 different programs (1 x 2 CPLD + 1 x 1 CPLD), can I still use a single JTAG connector? We are very tight in real estate in the PCB, so having 3 JTAG connectors is not viable.

My current implementation of the JTAG and CPLD's in a high level is something like the image attached.



Any help provided will be highly appreciated!


Jonathan
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Printing Schematic in Quartus Prime 17.1.1

March 13, 2018, 6:17 am
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Good morning,

I have been doing some research on how to effectively print a schematic in Quartus Prime 17.1.1, but have not found a concrete answer. I found how to set up a page for 11" x 17" paper, but my schematic is still too big for that page size. Also, I found that Quartus II was able to divide the schematic in different pages (to be printed, not schematic sheets), but I cannot find that option in my version.

Given that, is there a way they I can split the schematic in multiple pages and be able to print it? I need to provide a schematic to be reviewed by my project team, but the methods I have right now will not work for me.

Thanks in advance!


Jonathan
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Ethernet ip trouble

March 13, 2018, 7:33 am
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Hi
I'm trying to boot the DE10 Nano's GHRD Example to my board but when I launch putty to copy the files the ethernet conection is lost.
I need a router or why it doesn't work the conection with the pc host. I've tried with two computers.

Sombody can help me please
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Error (169281): There are 469 IO input pads in the design

March 13, 2018, 8:56 am
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I get the following error message in Quartus when I compile my code:

Error (169281): There are 469 IO input pads in the design, but only 293 IO input pad locations available on the device.

However it works fine when I compile the same VHDL code in VT System FPGA Manager (Vector tool).

I am using Cyclone IV E EP4CE75F23I8L.

Since I am using a Vector board there are a number of IO ports that are set by default in the main HDL file. Do I get this error because Quartus does not know which board I intend to use?

Also, is the error message referring to the IO pads available on the FPGA or on the board?
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DE1 SoC hangs when programmed

March 13, 2018, 11:02 am
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Hi!

I have made a small program to make a led flicker and programmed the FPGA with it. Everything went fine. However I have another project which I used to build in a previous version of quartus II and program it on an older cyclone II FPGA. I build this same project with the newer quartus II version 17.1 with no errors. However, when I try to program the cyclone V the following happens: the process starts properly, reaches 86% and then fails. After that I have to power off and on the FPGA so that it works again.

Any idea would be appreciated. Thank you.
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License problem with custom QSYS component.

March 13, 2018, 11:27 am
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Hi,
I made custom QSYS component in QSYS Quartus II 16.1.
To validate it I open project in QUARTUS II 17.1 Lite Edition. During compilation process I received the message:
...x_ctrl/synthesis/submudules/x_ctrl_cpu_cpu.v is OpenCore Plus time-limited file. Remove the unlicenses cores or obtain license for those OpenCore Plus time-limited IP cores.
All design is my one. How can I avoid these problems?
Best Regards,Tgel.
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MAx 10, External SRAM

March 13, 2018, 12:58 pm
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Hello, I connected an SRAM to MAX10.
To control I wrote a very simple IP that simply remap internal Avalon-MM signals and do a tristate of data bus lines.
This doesn't work event at low data rates.Checking with a Logic Analyzer and scope too signals seems to be ok.
Again I rewrote using a state machine, all signals timing got from state, this slow design added some delay to both control and data sampling, again no way to get it working.
ON both test Address bus, read write bus control are ok but not data on memory bus.
Ram part is: AS7C34098A
Code can be posted or attached here.
Thank in advance for hint or help
Roberto
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Booting Linux on Cyclone V DE1-SoC

March 13, 2018, 5:57 pm
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Hello, I am trying to get a basic Linux that I built with Yocto to boot on my DE1-SoC board.

I followed the directions here: https://rocketboards.org/foswiki/Doc...WithMetaAltera

I now have the following files in my build/deploy/images/cyclone5 directory.

core-image-minimal-cyclone5-20180312013803.rootfs.cpio
u-boot-cyclone5.img
core-image-minimal-cyclone5-20180312013803.rootfs.ext3
u-boot-spl-cyclone5
core-image-minimal-cyclone5-20180312013803.rootfs.manifest
u-boot-spl-cyclone5-2013.01.01-r0
core-image-minimal-cyclone5-20180312013803.rootfs.tar.gz
u-boot-spl-cyclone5-2013.01.01-r0.bin
core-image-minimal-cyclone5.cpio
u-boot-spl-cyclone5.bin
core-image-minimal-cyclone5.ext3
zImage
core-image-minimal-cyclone5.manifest
zImage--4.15+git0+1d50e4d026-r0-cyclone5-20180310225044.bin
core-image-minimal-cyclone5.tar.gz
zImage--4.15+git0+1d50e4d026-r0-socfpga_cyclone5_de0_sockit-20180310225044.dtb
modules--4.15+git0+1d50e4d026-r0-cyclone5-20180310225044.tgz
zImage--4.15+git0+1d50e4d026-r0-socfpga_cyclone5_socdk-20180310225044.dtb
modules-cyclone5.tgz
zImage--4.15+git0+1d50e4d026-r0-socfpga_cyclone5_sockit-20180310225044.dtb
README_-_DO_NOT_DELETE_FILES_IN_THIS_DIRECTORY.txt
zImage--4.15+git0+1d50e4d026-r0-socfpga_cyclone5_socrates-20180310225044.dtb
u-boot-cyclone5
zImage-cyclone5.bin
u-boot-cyclone5-2013.01.01-r0
zImage-socfpga_cyclone5_de0_sockit.dtb
u-boot-cyclone5-2013.01.01-r0.bin
zImage-socfpga_cyclone5_socdk.dtb
u-boot-cyclone5-2013.01.01-r0.img
zImage-socfpga_cyclone5_sockit.dtb
u-boot-cyclone5.bin
zImage-socfpga_cyclone5_socrates.dtb

I am trying to figure out what to do with these to put them on my SD Card to boot. I am given to understand that the first partition should be a FAT32 for u-boot, device-tree, and zImage and the second should be an ext4 for the rootfs.

Has anyone been able to go through this guide and put the right file on an SD Card to boot it on Terasic DE1-SoC?
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abnormal hardware resource usage

March 13, 2018, 6:56 pm
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Can anyone tell me why my resource usage increase non-linearly when I double parallelism.

I have set KERNEL_PARALLEL=64, FILTER_PARALLEL=8, so I expect every clock will have 64x8=512 MAC.
and report.html report that

ALUTs, FF, RAM, DSP
32-bit Integer Add (x640) 15981 0 0 0
32-bit Integer Multiply (x512) 0 0 0 256
As expect have 512 Multiply, my question is , why only use 256 DSP? and why 32 bit Add is 640?

------------------------------------------
Furthermore, when I set KERNEL_PARALLEL=64, FILTER_PARALLEL=16, the resource usage become very large, that I can't understand.
How to explain this usage?

Add(x13986) 456398 0 0 0
And(x13248) 145728 0 0 0
Mul(x00610) 000000 0 0 305


Code:
typedef struct{
    char kk[KERNEL_PARALLEL];
} kernel_parallel;


typedef struct{
    kernel_parallel ff[FILTER_PARALLEL];
} filter_parallel;

__kernel(){

    int result_buffer[KERNEL_PARALLEL];
    filter_parallel w_in,data_in;

    #pragma unroll
    for(int i=0; i<FILTER_PARALLEL; i++){
        #pragma unroll
        for(int j=0; j<KERNEL_PARALLEL; j++){
    ​        result_buffer[j] +=  w_in.ff[i].kk[j] * data_in.ff[i].kk[j];
        }
    }
}
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Altera DE2: LVDS bit alignment issue

March 13, 2018, 8:43 pm
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I'm trying to verify whether my FPGA board (Altera DE2) can support LVDS. For this purpose, I set up a simple system to test it, using an ALTLVDS_TX module to output to a GPIO pair, which is then connected to an input GPIO pair and corresponding ALTLVDS_RX module. The data I'm transmitting is a simple 8-bit up counter, at 100 Mbps, nothing too speedy. However, I'm experiencing bit alignment issues, where the received bits are the same as the transmitted ones, but shifted. I wouldn't mind if the shift was by a multiple of 8, but right now it's by 21 bits, so my words are coming out corrupted.

Here are some waveforms and the circuit schematic
Here's the transmitter settings.
Here's the receiver settings.


The most obvious thing I tried to change is the phase alignment alignment of tx_in WRT tx_inclock, or rx_in WRT rx_inclock, but the only option I get is 0.
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Can I safely ignore these hierarchy connectivity warnings?

March 14, 2018, 3:24 am
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Hello, I have the following problem that I have not been able to solve by searching the Forums:

I have a system with a Nios2 gen2 processor and the nios_custom_instr_floating_point custom instruction. This is the only custom instruction IP used.
On compilation I get the warning "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder"
When I check the Connectivity Checks report I see the following 3 warnings (I include the reset_req Info for completeness):

Code:
Port                    Type    Severity    Details
reset_req                Input    Info        Stuck at GND
A_ci_multi_estatus    Output    Warning        Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.
A_ci_multi_ipending    Output    Warning        Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.
A_ci_multi_status        Output    Warning        Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.
I don't know how to determine if these signals are really needed in the design or have been left unconnected because they are not needed.
Does anybody know if I can safely ignore them and why?
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Error: Node instance "inst" instantiates undefined entity "XXX"

March 14, 2018, 3:49 am
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Hi all,
I have created the symbol file from the verilog code in Quartus. Then i have added verilog file and bsf file into Quartus --> library. Then i have created new project for adding my block design file and started synthesis. Its throwing an error

"Error (12006): Node instance "inst" instantiates undefined entity "count"
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 1 error, 0 warnings

Is there anyone having idea about this error. Please look over the attachment and guide me.
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Error:I/O std LVDS on output I/O pin cannot have Termination logic option setting

March 14, 2018, 5:26 am
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Hi,

I have created simple schematic design [consists of 4-bit counter and Ibufout-diff [from IP catlog]. While compilation, it`s showing error.

one more issue is, i have assigned only 4 pins[3..0], but in pin planner its taking extra pin count. I dont know why.

Please look over my design and Pin planner diagram.
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Building hello_world issue with embedded_command_shell

March 14, 2018, 6:36 am
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Hi, I have tried building hello_world host as well as other examples from de10_nano BSP. However, none of them were built successfully.
They all met the same question:

$ make
arm-linux-gnueabihf-g++: 閿欒锛?libpath:E:/intelFPGA/17.1/hld/host/windows64/l
ib锛欼nvalid argument
arm-linux-gnueabihf-g++: 閿欒锛歄penCL.lib锛歂o such file or directory
make: *** [bin/hello_world] Error 1

Please help me get rid of the issue above. Thanks a lot!
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Working with differents schematics

March 14, 2018, 7:47 am
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Hi, Im working with different schematics, and im wondering to know , if its possible to join them as, for instance, you can do it con cad soft like Altium, where you use different sheet and work with hierarchical block in the same project.

a solution would be, embbed many blocks and generate a bigger block with them iners?


thanks
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illegal inout port connections in vsim 3053

March 14, 2018, 8:59 am
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While simulating my Verilog testbench I get this error on ny inout ports. What datatypes should they be so that I don&#39;t get this error. Also I am assigning some of these inouts in initial blocks; how should I do?

Please advise. Many thanks
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Arria 10 Dev Kit - Possibly corrupted board during factory reset - how to correct

March 14, 2018, 10:06 am
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I started work on an Arria 10 Dev Kit today (p/n 10AX115S). I was following directions in the user guide and decided it would be good to start with a factory reset (this board was used previously in my organization by a former engineer).

I originally started the BoardTestSystem.exe GUI and followed the process to do a factory restore. In the middle of the restore, it ocurred to me that I might not have set the MSEL switches correct (there seemed to be some confusion in the users guide on how to set them: 100 or 011...). Anyway, as it was restoring, I hit 'cancel' to get out of it and start over. At that point, the fan started to spin at a *much* higher rate. And, then when I went back to restart BoardTestSystem.exe, I get an error dialog that says:

"Failed to register GUI application!
Please make sure... "

I fear that I have corrupted, I guess, the Flash memory. Is there a way that I can recover from this?
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Arria 10 FPGA with urjtag

March 14, 2018, 10:19 am
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I design a board with altera Arria 10 FPGA "10AX115N3F40I2SG" i can successfully program Fpga with altera bus blaster 2. Now I want to program board by using bus blaster V3, i tried a lot but failed to program it. Urjtag can not recognize the bsdl file. I download the bsdl file from altera website. I wonder did i downloaded correct file, the file i downloaded was "10AX115NF40". Any help can be appreciated to pull me out from this problem thanks. I attached the urjtag command line image as well.
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University Looking to Update Old Hardware

March 14, 2018, 11:07 am
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I am the Electrical Engineering Lab supervisor at a University in Pennsylvania and we are looking to update our PLD collection, programming interface, software (well basically everything) related to PLDs and CPLDs. We have, many years ago before I took this job, used the EPM7160SCL84-10, EPM7032LC44-15 and the EP610DC-35 chips, but have not been able to for several years since the software and hardware that programs them runs on Windows XP and needs to check the license before running and since XP is no longer secure our IT department no longer allows it on the network meaning we can no longer use the current set up.

Ideally we want to avoid dev boards and would like to program individual chips that can be put on a breadboard (these are the professor's requests). We want to use these within the context of a first semester digital class (undergrad) where the students can easily program simple circuits that will drive a 7 segment display, for example. The professor wants to expose the students, who build the circuits throughout the semester using 7400 series chips for their class labs, a more modern way of implimenting logic.

I have been looking around for some time now for the solution and have not been able to find exactly what we want. I want to know if anyone knows of a solution that will fill our needs: ability to program individual chips that can be breadboarded (adapter boards can be used with TQFPs), TTL compatible logic levels would be preferred, and ease of use (they won't have all semester to learn how to program).

Any help would be greatly appreciated.
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