I require some assistance with Quartus Pro Edition (17.1) incremental compilation.
I have a project called 'simple'. It has a single top VHDL file called simple.vhd:
Code:
library ieee;
use ieee.std_logic_1164.all ;
entity simple is
port (
input: in bit;
clk : in std_logic ;
output :out bit
);
end simple;
architecture rtl of simple is
component sub
port (
input: in bit;
clk : in std_logic ;
output :out bit
);
end component;
begin
SC: component sub
port map(
input => input,
clk => clk,
output => output
);
end rtl;
The 'sub' module is a very simple module that was compiled
in a separate project. It has a single top VHDL file called sub.vhd
:
Code:
library ieee;
use ieee.std_logic_1164.all ;
entity sub is
port (
input: in bit;
clk : in std_logic ;
output :out bit
);
end sub;
architecture rtl of sub is
begin
output <= input;
end rtl;
In the 'simple' project, I wish to include only the component declaration, component instantiation, and QDB file for 'sub'. The component declaration and instantiations are shown in the VHDL above. I do
not want to include the entity declaration here because the entity's inclusion is generally not required when reusing a synthesized netlist (verified in Quartus Standard as well as other HDL compilation tools).
What I mean here, is that generally all that is required for reusing a synthesized netlist, is the netlist itself and a component declaration (
i.e. the stub). So, I should not have to include an entity declaration in the project when all I wish to do is use a QDB file that contains the already-synthesized 'sub' module.
I have gone through all of Intel/Altera's Incremental Block-Based Compilation training, and I have not been able to determine how to have 'sub' be truly just a netlist and a component-declaration stub file.
I am having the following issues.
1. I cannot reuse the synthesized 'sub' module if it is the top-module of its project.
- There must be something wrong here. It does not make sense that I would have to create a wrapper module for 'sub' in its project just so I can reuse the synthesized results of 'sub' elsewhere....
- I tried exporting the entire 'sub' project via Project -> Export Design, but this did not work because when I imported it in the 'simple' project, it wanted the QDB to represent the 'simple' project itself, not a submodule or partition of the 'simple' project. Similar problem when I used command line quartus_cdb to export the root_partition.
2. I still have problems even if I create a wrapper module for 'sub', set 'sub' as a design partition with Preservation Level=synthesized, and export that partition to a QDB:
- How can I tell the 'simple' project that it has a sub-module that should be a pre-synthesized partition? I try to run Analysis & Elaboration, but it fails with "Error(16045): Instance "SC" instantiates undefined entity "sub"." So, there is no module hierarchy for me to set design partitions.
- I manually modified the QSF to set the 'sub' module as a partition with a QDB:
set_instance_assignment -name PARTITION sub -to SC -entity simple
set_instance_assignment -name PRESERVE synthesized -to SC -entity simple
set_instance_assignment -name QDB_FILE_PARTITION /data/workspace/sub.qdb -to SC -entity simple
but this was not successful and resulted in the same error
- Finally, I tried adding the entity declaration for 'sub' (which I absolutely should not have to do in 'simple' as it is not required in any other HDL compilation tools). I used the same 3 partition assignments in the above bullet, and I see the following error:
Error(19326): The partition "sub" is loaded from a Partition Database File (.qdb) and is set to preserve with a Preservation Level assignment. These two preservation types cannot be combined.
- It seems like I can get different errors if I do things in different orders.... I was able to get a seg fault by then commenting out the 'sub' entity declaration
Any help here is much appreciated. Ultimately what I would like to do is synthesize 'sub' to a netlist. 'sub' should ideally be the
top level of its own project. Again I should not have to put a dummy wrapper module around 'sub' just to get a reusable netlist.... In Quartus Standard, this is as simple as synthesizing a project to a QXP (similar flow is seen in other tools as well). I would then like to instantiate 'sub' in 'simple' with just a component declaration and instantiation
without the entity declaration as is possible with Quartus Standard and other tools. Finally, I would like to be able to synthesize 'simple' and proceed from there.
Thanks,
dbanks12