What are some major differences between BSPs from various vendors? Currently I am using a10gx board with a10ref bsp. Are there differences in only in global memory BW?
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Differences among various BSPs
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DE2-115 board with DCC AD/DA daughter card
Hi all.
I am trying to implement a DDS with altera DE2-115 board. I want to use only the DAC of the daughter card. My codes run, no errors, in modelsim I can see the input thats gonna go in the hsmc interface. Its all fine, but I get no output from the DAC output co-ax when I connect it to an oscilloscope.
I downloaded the DE2-115+DCC AD/DA demo that was available in the website. That runs fine, and I get the output from the DAC output channel as its supposed to. But when I input from my file I dont get anything out. Nothing. Not even a wrong signal either. Just noise. I should get something!
Can anyone provide any insight in this? Thanks in advance. Any suggestion would be helpful.
I am trying to implement a DDS with altera DE2-115 board. I want to use only the DAC of the daughter card. My codes run, no errors, in modelsim I can see the input thats gonna go in the hsmc interface. Its all fine, but I get no output from the DAC output co-ax when I connect it to an oscilloscope.
I downloaded the DE2-115+DCC AD/DA demo that was available in the website. That runs fine, and I get the output from the DAC output channel as its supposed to. But when I input from my file I dont get anything out. Nothing. Not even a wrong signal either. Just noise. I should get something!
Can anyone provide any insight in this? Thanks in advance. Any suggestion would be helpful.
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How can Nios II read an external FIFO as if it was Avalon MM component?
A FIFO shall feed data to the Nios II. As expected, it exposes q, rdreq and empty signals. These can be easily mapped to Avalon ST compatible signals by merely inverting empty signal to generate the Avalon ST valid signal.
Now the question is, what do I do next so the Nios II Master can interface with this FIFO as if it was an Avalon MM slave? Certainly this shall require some sort of conversion between Avalon ST to Avalon MM as if the Nios II master was reading a FIFO inside the Qsys system.
Is this possible?
Now the question is, what do I do next so the Nios II Master can interface with this FIFO as if it was an Avalon MM slave? Certainly this shall require some sort of conversion between Avalon ST to Avalon MM as if the Nios II master was reading a FIFO inside the Qsys system.
Is this possible?
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Swicthing between LVDS and LVCMOS
Hi, Do FPGA IC's pin able to switching between LVDS and LVCMOS in one program?
If yes, how do I configure it?
Let said I used one pin to switch IO pins.
When logic '1', all my IO pins become LVDS pair.
When logic '0',all my IO pins become LVMOS pin.
If yes, how do I configure it?
Let said I used one pin to switch IO pins.
When logic '1', all my IO pins become LVDS pair.
When logic '0',all my IO pins become LVMOS pin.
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Does PCIe HD IP include the PHY IP Core? How to pin assignment for differential?
Hi all,
I have one starter Kit of Arria V. And I want to realize one application with <Avalon-MM Arria V hard HD IP for PCIe>.
My 2 questions:
1. Does <Avalon-MM Arria V hard HD IP for PCIe> include the PHY IP Core?
Need I add the additional PHY IP Core for <Avalon-MM Arria V hard HD IP for PCIe>?
2. In the top-level entity of PHY IP Core of PCIe, which signals are for differential couples? How should I do pin-assignment for the differential?
I cannot find the pair of +/- signals in the interface PHY IP Core of PCIe. It is confusion.
I wait your professional answer.
Thanks in advance.
I have one starter Kit of Arria V. And I want to realize one application with <Avalon-MM Arria V hard HD IP for PCIe>.
My 2 questions:
1. Does <Avalon-MM Arria V hard HD IP for PCIe> include the PHY IP Core?
Need I add the additional PHY IP Core for <Avalon-MM Arria V hard HD IP for PCIe>?
2. In the top-level entity of PHY IP Core of PCIe, which signals are for differential couples? How should I do pin-assignment for the differential?
I cannot find the pair of +/- signals in the interface PHY IP Core of PCIe. It is confusion.
I wait your professional answer.
Thanks in advance.
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MAX-10: IP core for UFM
I have instantiated the Altera on-chip flash IP core to use the MAX-10's UFM, but Quartus does not generate programming files since the one of the modules of the IP core is encrypted. I tried to use the IP core with Open core feature enabled (Evaluation Mode) but Quartus still does not generate the programming files. Any idea what may have gone wrong? Besides can anyone please also share where to contact Intel/Altera to get a quote for IP cores?
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FIR I vs FIR II
I have used FIR I in a couple of projects (Quartus 9.1). I am considering upgrading to the latest Quartus and buying FIR II. In FIR I there is an "Edit Coefficients" button to open a configuration window where you can select the type of filter (e.g. Blackman) and enter the required frequency cut-off. This seems to have disappeared in FIR II? Are you expected to use another tool to generate the Coefficients?
I do not have MATLAB, but do have the Microchip dspWorks filter tool. Is this my best option going forward?
If this feature has ben removed wasn't this a step backwards?
I do not have MATLAB, but do have the Microchip dspWorks filter tool. Is this my best option going forward?
If this feature has ben removed wasn't this a step backwards?
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generating .hex programming file from Quartus Prime
How to generate .hex programming file from Quartus Prime software?Thank you in advance.
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TimeQuest: constraining inout ports
Hi all,
this is probably a question to Rysc (as he's the author of the TimeQuest User Guide) but of course any helpful answer from anybody is more than welcome as well.
Discontent with my past understanding of timing constraints (I was just fiddling with them to the extend of getting my designs running but wouldn't really claim I've understood them), I decided to work through the TimeQuest User Guide. I guess I know have lot more thorough understanding regarding them (@Rysc: thank you for enlightment, btw., really appreciated).
Then I decided to test my newly acquired knowledge: set up a (really simple) design and started to constrain it by the book. My toplevel entity (stripped down from a real project) looks like this:
(if it matters, this is a Cyclone III attached to a 33MHz FreeScale FlexBus interface, the architecture is just a single 32 bit register that can be read and written through the FlexBus interface)
created clocks and virtual clocks:
defined ports:
(FB_AD is an inout port, i.e. the multiplexed address/data bus of the FlexBus, therefore it appears in both lists)
and constrained them (according to the guide):
So far, so good. Works as expected up to this point (I'm well aware that I'm not finished and still need to add reasonable outside timing consumes).
But there is one thing that concerns me: as soon as I constrain the inout bus both directions, I get a ridiculously low restricted Fmax:
and have no idea where this is coming from. For now, I tell TimeQuest that the outside world works in zero time and doesn't require any timing margin. Even if I replace the min and max delays with more "real" numbers, restricted Fmax stays at (exactly) 5.81 MHz.
Does anyone know where this is coming from or what I'm supposed to do with that? Is TimeQuest assuming a toggle rate for a "virtual register" outside the FPGA?
I might have overlooked something in the TimeQuest User Guide but didn't find anything specific on inout signals.
For now, I helped myself with a second virtual clock (one for in and one for out). Once I do that, the numbers look a lot more reasonable. But is that the right way to handle this case?
Thanks in advance for any enlightening answers.
[edit: forgot to mention the design works fine with 33 MHz even if TimeQuest says it doesn't; also there is nothing showing up "red" in timing reports]
this is probably a question to Rysc (as he's the author of the TimeQuest User Guide) but of course any helpful answer from anybody is more than welcome as well.
Discontent with my past understanding of timing constraints (I was just fiddling with them to the extend of getting my designs running but wouldn't really claim I've understood them), I decided to work through the TimeQuest User Guide. I guess I know have lot more thorough understanding regarding them (@Rysc: thank you for enlightment, btw., really appreciated).
Then I decided to test my newly acquired knowledge: set up a (really simple) design and started to constrain it by the book. My toplevel entity (stripped down from a real project) looks like this:
Code:
entity simple is
port
(
CLK_MAIN : in std_logic;
RESETn : in std_logic;
-- FlexBus signals
FB_AD : inout std_logic_vector(31 downto 0);
FB_ALE : in std_logic;
FB_SIZE : in std_logic_vector(1 downto 0);
FB_CSn : in std_logic_vector(3 downto 1);
FB_BURSTn : in std_logic;
FB_OEn,
FB_WRn : in std_logic;
FB_TAn : out std_logic
);
end entity simple;created clocks and virtual clocks:
Code:
set period [expr roundto(1000000.0 / 33000.0, 3)]
create_clock -period $period -name CLK_MAIN [get_ports {CLK_MAIN}]
create_clock -period $period -name virt_clk_mainCode:
set flexbus_in_ports
[list FB_AD[*] FB_ALE FB_OEn FB_WRn]
set flexbus_out_ports
[list FB_AD[*] FB_TAn]and constrained them (according to the guide):
Code:
foreach in_port $flexbus_in_ports {
set_input_delay -clock virt_clk_main -min -0 $in_port
set_input_delay -clock virt_clk_main -max 0 $in_port
}
foreach out_port $flexbus_out_ports {
set_output_delay -clock virt_clk_main -min -0 $out_port
set_output_delay -clock virt_clk_main -max 0 $out_port
}But there is one thing that concerns me: as soon as I constrain the inout bus both directions, I get a ridiculously low restricted Fmax:
Code:
+-----------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary ;
+------------+-----------------+---------------+------------------------------------------------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+------------+-----------------+---------------+------------------------------------------------+
; 61.66 MHz ; 5.81 MHz ; virt_clk_main ; limit due to minimum period restriction (tmin) ;
; 141.96 MHz ; 141.96 MHz ; CLK_MAIN ; ;
+------------+-----------------+---------------+------------------------------------------------+Does anyone know where this is coming from or what I'm supposed to do with that? Is TimeQuest assuming a toggle rate for a "virtual register" outside the FPGA?
I might have overlooked something in the TimeQuest User Guide but didn't find anything specific on inout signals.
For now, I helped myself with a second virtual clock (one for in and one for out). Once I do that, the numbers look a lot more reasonable. But is that the right way to handle this case?
Thanks in advance for any enlightening answers.
[edit: forgot to mention the design works fine with 33 MHz even if TimeQuest says it doesn't; also there is nothing showing up "red" in timing reports]
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↧
Example Design compilation does not run on FPGA (newbie needs help)
Hello there,
I am currently trying to get into OpenCL Programming for FPGAs.
I followed Intels "aocl_c5soc_getting_started" guide (I've got a DE10-Standard).
I eventually got the emulation up and running, but i have huge probelms with the
cross-compilation of the host aswell as the actual Kernel compilation.
I compiled the Kernel with the environment Variables set as described in the guide.
This command exited after around 30 minutes with 2 warnings and 0 errors.
The Image which i downloaded from Terasic already contains a working kernel and
executable so i tried to swap out their kernel with mine and it did no longer work. (At this
point I was not able to compile the host so I thought to give the swap a try to verify wether
the kernel is working correctly)
So now onto the Host compiling problem. So i start by setting up the environment variables
as before and ran make, which had a warning about libacl_emulator_kernel_rt.so missing.
Now that i had the kernel and the host i tried running it on the FPGA and got error message
I found this guide on Youtube https://www.youtube.com/watch?v=npEU...=RD4PUKzI14mLY
and he switch into the embedded shell for compiling, but after doing
so I only got another error Message stating
which is probably because the cc1plus in the path is a 32bit ELF.
Further Information:
I am Running in Ubuntu 16.04 and use IntelFPGA OpencSDK 18.0.
The Board I use is the Terasic DE10-Standard (Cyclone 5 SoC)
Environment Variables are set up as follows
Thanks and kind regards, Daniel.
I am currently trying to get into OpenCL Programming for FPGAs.
I followed Intels "aocl_c5soc_getting_started" guide (I've got a DE10-Standard).
I eventually got the emulation up and running, but i have huge probelms with the
cross-compilation of the host aswell as the actual Kernel compilation.
I compiled the Kernel with the environment Variables set as described in the guide.
Code:
aoc -board=c5soc_sharedonly device/vector_add.cl -o bin/vector_add.aocxThe Image which i downloaded from Terasic already contains a working kernel and
executable so i tried to swap out their kernel with mine and it did no longer work. (At this
point I was not able to compile the host so I thought to give the swap a try to verify wether
the kernel is working correctly)
So now onto the Host compiling problem. So i start by setting up the environment variables
as before and ran make, which had a warning about libacl_emulator_kernel_rt.so missing.
Now that i had the kernel and the host i tried running it on the FPGA and got error message
Code:
./host: error while loading shared libraries: libintel_soc32_mmd.so: cannot open
shared object file: No such file or directoryand he switch into the embedded shell for compiling, but after doing
so I only got another error Message stating
Code:
arm-linux-gnueabihf-g++: error trying to exec 'cc1plus':
execvp: file or directory not foundFurther Information:
I am Running in Ubuntu 16.04 and use IntelFPGA OpencSDK 18.0.
The Board I use is the Terasic DE10-Standard (Cyclone 5 SoC)
Environment Variables are set up as follows
Code:
$ cat exports
export ALTERAOCLSDKROOT="/home/daniel/intelFPGA/18.0/hld"
export INTELFPGAOCLSDKROOT=$ALTERAOCLSDKROOT
export QUARTUS_ROOTDIR_OVERRIDE="/home/daniel/intelFPGA/18.0/quartus"
export AOCL_BOARD_PACKAGE_ROOT=$ALTERAOCLSDKROOT/board/c5soc
export PATH=$ALTERAOCLSDKROOT/bin:$QUARTUS_ROOTDIR_OVERRIDE:$PATH
export LD_LIBRARY_PATH=$ALTERAOCLSDKROOT/host/linux64/lib:$AOCL_BOARD_PACKAGE_ROOT/linux64/lib:$LD_LIBRARY_PATH
export LD_LIBRARY_PATH=$ALTERAOCLSDKROOT/board/s5_ref/linux64/lib:$LD_LIBRARY_PATH
$ source exports↧
What is the use/relevence of inst in .bdf files.
I'm just starting to use Quartus with Block Design Files -- very impressed. Coming from a KiCAD background it seems natural.
Two things have me puzzled:
What is the relevance on "inst" in each block. As I add components the number seems to increase. Is it just a way of identifying a block for debugging etc. or is there more to it.
Second, its unclear to me what the relevance/difference between
"Analysis & Synthesis" and
"Fitter (Place & Route)" are.
Do I use both, one or none before doing a compile, none, once, or every time.
Thanks in advance guys, hopefully questions like these will be helpful to other newbies.
John
Two things have me puzzled:
What is the relevance on "inst" in each block. As I add components the number seems to increase. Is it just a way of identifying a block for debugging etc. or is there more to it.
Second, its unclear to me what the relevance/difference between
"Analysis & Synthesis" and
"Fitter (Place & Route)" are.
Do I use both, one or none before doing a compile, none, once, or every time.
Thanks in advance guys, hopefully questions like these will be helpful to other newbies.
John
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Max10 PLL input clock switchover example?
Hi
I read max10 datasheet and it says that its PLLs support input clock switchover. I tried to used ALTPLL IP-core in Qsys(Platform design) to configure this feature but the "Clock Switchover"-Tab is always inactive and I couldn't find the way to activate it.
Is there any example for using PLL input clockswitchover in Max10?
Thanks alot.
Bien
I read max10 datasheet and it says that its PLLs support input clock switchover. I tried to used ALTPLL IP-core in Qsys(Platform design) to configure this feature but the "Clock Switchover"-Tab is always inactive and I couldn't find the way to activate it.
Is there any example for using PLL input clockswitchover in Max10?
Thanks alot.
Bien
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Error (10759) when compile boardtest.cl kernel
when i run to compile boardtest.cl kernel, have the bellow error : error (10759) the verilog hdl error at boardtest_system.v :object kclk_finish declared in a list of port decralation cannot be redeclared within the module body file: e:/intelFPGA/17.1/hld/board/terasic/de1soc/example/boardtest/bin/boardtest/system/systhesis/submodule/boardtest_system.v line 488
did that file generate automatically?why still this error
did that file generate automatically?why still this error
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↧
Using of Restrict keyword
Hi All,
We have implemented 4 kernels in one .cl file. We are trying to optimize the kernels. So gone through AOCL best practices guide, it suggests the usage of restrict keyword in pointer arguments whenever possible. So we have used for all 4 kernels. But resource utilization has increased from 58% to 135%. Instead, if we use for one kernel, then it is giving performance (kernel execution time is decreased from 98msec to 50msec). Is there any alternative for restrict keyword?
Thanks
We have implemented 4 kernels in one .cl file. We are trying to optimize the kernels. So gone through AOCL best practices guide, it suggests the usage of restrict keyword in pointer arguments whenever possible. So we have used for all 4 kernels. But resource utilization has increased from 58% to 135%. Instead, if we use for one kernel, then it is giving performance (kernel execution time is decreased from 98msec to 50msec). Is there any alternative for restrict keyword?
Thanks
↧
clflush or any openCL API is taking more time once kernel execution is completed.
In function1(), we are launching kernel, but we are not waiting for kernel completion. After kernel launch, some processing is happening on CPU which takes around 300msec. While processing on CPU we have triggered for the kernel execution status along with timer. It is showing status as running for few iterations and time taken by clFlush is negligible. Once kernel execution is completed clFlush is consuming 6711 micro sec(Instead of clfinish, if we have clenqueuereadbuffer it is also consuming the same time). Why is it consuming more time once the execution is completed? Is there any alternate method to reduce the time?
void function1()
{
printf("In function-1\n");
...
err = clEnqueueTask(commandQueue[0], kernel, 0, NULL, &kernel_event[0]);
if (CL_SUCCESS != err) {
printf("Error in clEnqueueTask kernel-1 %d\n\n", err);
exit(-1);
}
}
void function2()
{
printf("In function-2\n");
struct timeval start_timer, end_timer;
gettimeofday(&start_timer, NULL);
err = clEnqueueReadBuffer(commandQueue[0], dstOut1, CL_TRUE, 0, 120 * 23 * sizeof(cl_short2), output1, 0, NULL, NULL);
if (CL_SUCCESS != err) {
printf("Error in clEnqueueReadBuffer dstOut1 %d\n", err);
exit(-1);
}
gettimeofday(&end_timer, NULL);
time_taken = ((end_timer.tv_sec * 1000000 + end_timer.tv_usec) - (start_timer.tv_sec * 1000000 + start_timer.tv_usec));
printf("Time taken by clEnqueueReadBuffer-1 %ld\n", time_taken);
gettimeofday(&start_timer, NULL);
err = clEnqueueReadBuffer(commandQueue[0], dstOut2, CL_TRUE, 0, 120 * 23 * sizeof(cl_short2), output2, 0, NULL, NULL);
if (CL_SUCCESS != err) {
printf("Error in clEnqueueReadBuffer dstOut2 %d\n", err);
exit(-1);
}
gettimeofday(&end_timer, NULL);
time_taken = ((end_timer.tv_sec * 1000000 + end_timer.tv_usec) - (start_timer.tv_sec * 1000000 + start_timer.tv_usec));
printf("Time taken by clEnqueueReadBuffer-2 %ld\n", time_taken);
//launching another kernel
err = clEnqueueTask(commandQueue[0], kernel, 0, NULL, &kernel_event[0]);
if (CL_SUCCESS != err) {
printf("Error in clEnqueueTask kernel-1 %d\n\n", err);
exit(-1);
}
}
int main()
{
for(int i = 0; i < 100; i++)
{
if(i == 0)
function1();
else
function2();
/* processing on cpu */
for(int id = 0; id < 1000; id++)
{
/* processing on cpu */
struct timeval begin_cq, end_cq;
gettimeofday(&begin_cq, NULL);
cl_int res, status;
res = clGetEventInfo(kernel_event[0], CL_EVENT_COMMAND_EXECUTION_STATUS, sizeof(cl_int), &status, NULL);
switch (status)
{
case CL_QUEUED:
printf("Execution Status: Queued\n");
break;
case CL_SUBMITTED:
printf("Execution Status: Submitted\n");
break;
case CL_RUNNING:
printf("Execution Status: Running\n");
break;
case CL_COMPLETE:
printf("Execution Status: Completed\n");
break;
default:
printf("Execution Status: Error (%d)\n", status);
break;
}
clFlush(commandQueue[0]);
gettimeofday(&end_cq, NULL);
long time_taken_cq = ((end_cq.tv_sec * 1000000 + end_cq.tv_usec) - (begin_cq.tv_sec * 1000000 + begin_cq.tv_usec));
printf("Time taken by clFlush %ld micro sec\n", time_taken_cq);
}//for(id)
}//for(i)
return 0;
}
Output:
In function-1
Execution Status: Running
Time taken by clFlush 5 micro sec
Execution Status: Running
Time taken by clFlush 4 micro sec
Execution Status: Running
Time taken by clFlush 4 micro sec
Execution Status: Running
Time taken by clFlush 4 micro sec
Execution Status: Running
Time taken by clFlush 4 micro sec
Execution Status: Running
Time taken by clFlush 4 micro sec
Execution Status: Running
Time taken by clFlush 4 micro sec
Execution Status: Completed
Time taken by clFlush 6711 micro sec
Execution Status: Completed
Time taken by clFlush 1 micro sec
Execution Status: Completed
Time taken by clFlush 1 micro sec
Execution Status: Completed
Time taken by clFlush 2 micro sec
Execution Status: Completed
Time taken by clFlush 2 micro sec
Execution Status: Completed
Time taken by clFlush 2 micro sec
Execution Status: Completed
Time taken by clFlush 1 micro sec
Execution Status: Completed
Time taken by clFlush 2 micro sec
.
.
.
In function-2
.
.
.
Thanks, in advance
void function1()
{
printf("In function-1\n");
...
err = clEnqueueTask(commandQueue[0], kernel, 0, NULL, &kernel_event[0]);
if (CL_SUCCESS != err) {
printf("Error in clEnqueueTask kernel-1 %d\n\n", err);
exit(-1);
}
}
void function2()
{
printf("In function-2\n");
struct timeval start_timer, end_timer;
gettimeofday(&start_timer, NULL);
err = clEnqueueReadBuffer(commandQueue[0], dstOut1, CL_TRUE, 0, 120 * 23 * sizeof(cl_short2), output1, 0, NULL, NULL);
if (CL_SUCCESS != err) {
printf("Error in clEnqueueReadBuffer dstOut1 %d\n", err);
exit(-1);
}
gettimeofday(&end_timer, NULL);
time_taken = ((end_timer.tv_sec * 1000000 + end_timer.tv_usec) - (start_timer.tv_sec * 1000000 + start_timer.tv_usec));
printf("Time taken by clEnqueueReadBuffer-1 %ld\n", time_taken);
gettimeofday(&start_timer, NULL);
err = clEnqueueReadBuffer(commandQueue[0], dstOut2, CL_TRUE, 0, 120 * 23 * sizeof(cl_short2), output2, 0, NULL, NULL);
if (CL_SUCCESS != err) {
printf("Error in clEnqueueReadBuffer dstOut2 %d\n", err);
exit(-1);
}
gettimeofday(&end_timer, NULL);
time_taken = ((end_timer.tv_sec * 1000000 + end_timer.tv_usec) - (start_timer.tv_sec * 1000000 + start_timer.tv_usec));
printf("Time taken by clEnqueueReadBuffer-2 %ld\n", time_taken);
//launching another kernel
err = clEnqueueTask(commandQueue[0], kernel, 0, NULL, &kernel_event[0]);
if (CL_SUCCESS != err) {
printf("Error in clEnqueueTask kernel-1 %d\n\n", err);
exit(-1);
}
}
int main()
{
for(int i = 0; i < 100; i++)
{
if(i == 0)
function1();
else
function2();
/* processing on cpu */
for(int id = 0; id < 1000; id++)
{
/* processing on cpu */
struct timeval begin_cq, end_cq;
gettimeofday(&begin_cq, NULL);
cl_int res, status;
res = clGetEventInfo(kernel_event[0], CL_EVENT_COMMAND_EXECUTION_STATUS, sizeof(cl_int), &status, NULL);
switch (status)
{
case CL_QUEUED:
printf("Execution Status: Queued\n");
break;
case CL_SUBMITTED:
printf("Execution Status: Submitted\n");
break;
case CL_RUNNING:
printf("Execution Status: Running\n");
break;
case CL_COMPLETE:
printf("Execution Status: Completed\n");
break;
default:
printf("Execution Status: Error (%d)\n", status);
break;
}
clFlush(commandQueue[0]);
gettimeofday(&end_cq, NULL);
long time_taken_cq = ((end_cq.tv_sec * 1000000 + end_cq.tv_usec) - (begin_cq.tv_sec * 1000000 + begin_cq.tv_usec));
printf("Time taken by clFlush %ld micro sec\n", time_taken_cq);
}//for(id)
}//for(i)
return 0;
}
Output:
In function-1
Execution Status: Running
Time taken by clFlush 5 micro sec
Execution Status: Running
Time taken by clFlush 4 micro sec
Execution Status: Running
Time taken by clFlush 4 micro sec
Execution Status: Running
Time taken by clFlush 4 micro sec
Execution Status: Running
Time taken by clFlush 4 micro sec
Execution Status: Running
Time taken by clFlush 4 micro sec
Execution Status: Running
Time taken by clFlush 4 micro sec
Execution Status: Completed
Time taken by clFlush 6711 micro sec
Execution Status: Completed
Time taken by clFlush 1 micro sec
Execution Status: Completed
Time taken by clFlush 1 micro sec
Execution Status: Completed
Time taken by clFlush 2 micro sec
Execution Status: Completed
Time taken by clFlush 2 micro sec
Execution Status: Completed
Time taken by clFlush 2 micro sec
Execution Status: Completed
Time taken by clFlush 1 micro sec
Execution Status: Completed
Time taken by clFlush 2 micro sec
.
.
.
In function-2
.
.
.
Thanks, in advance
↧
CRC polinomial for Jumbo packs
Hi,
I'm currently investigating CRC polynomial for gigabit ethernet. I'm using CRC32 but I've noticed there was a mentioning about a different polynomial for jumbo packages. I couldn't find any further information with my searches. I
I'm currently investigating CRC polynomial for gigabit ethernet. I'm using CRC32 but I've noticed there was a mentioning about a different polynomial for jumbo packages. I couldn't find any further information with my searches. I
f you have knowledge about the subject and share it with me would appreciate it.
Thanks in advance. Have a nice day.
Thanks in advance. Have a nice day.
↧
Duplicate GPIO pins in Pin Planner
In the Pin Planner, I want to switch physical locations of my pin names. However, everything is in duplicate. I saw a publication of this issue in Quartus II and and read that this issue would not happen in the next version. Here I am in Quartus Prime and it is still happening. Do I just reassign each pair? Please advise.
↧
↧
FFT IP simulation : Warning: "sink_FIFO : scfifo" is not bound
Hello,
I am trying to simulate the Intel FFT IP in ModelSim Intel FPGA Starter Edition 10.5b, and I encounter a problem : the output "sink_ready" is X as soon as the reset is deasserted, and the fftpts_out is XXX... all the time.
Next, I explain first what I did, then I explain the problems observed. I put in attachment a screenshot of the simulation to show the problems described, the tcl files, and the entire folder with the quartus project and the ModelSim simulation under fft_example_tb.
Steps :
In my testbench, source_ready = 1, sink_error = 00, sink_valid/sop/eop = 0, inverse = 0, fftpts_in = 2048, sink_real/imag = 0 at the beginning.
Problems observed :
1. When starting the simulation, I see in the command window :
# Loading work.auk_dspip_avalon_streaming_block_sink(rtl)
# ** Warning: (vsim-3473) Component instance "sink_FIFO : scfifo" is not bound.
# Time: 0 ps Iteration: 0 Instance: /fft_tb/I_fft/fft_ii_0/auk_dspip_r22sdf_top_inst/sink_ctrl_inst File: ../fft/simulation/submodules/mentor/auk_dspip_avalon_streaming_block_sink.vhd
2. As said at the beginning, I have a problem with the following outputs :
When looking at the origin of the problem :
Since this block and these files are generated automatically, I never modified them.
I saw in this post that someone had a similar problem where an output of the FFT was always X, and it has been pointed out that it could be due to library files missing, and it was advised to check the msim_setup.tcl file generated automatically. However, all the files mentioned in msim_setup.tcl are also in my tcl file.
Do you have any clue about the origin of the problem ?
I am not familiar with the libraries and tcl files, so maybe this is where I made a mistake.
Thanks in advance.
Jérôme
I am trying to simulate the Intel FFT IP in ModelSim Intel FPGA Starter Edition 10.5b, and I encounter a problem : the output "sink_ready" is X as soon as the reset is deasserted, and the fftpts_out is XXX... all the time.
Next, I explain first what I did, then I explain the problems observed. I put in attachment a screenshot of the simulation to show the problems described, the tcl files, and the entire folder with the quartus project and the ModelSim simulation under fft_example_tb.
Steps :
- I create a Quartus project (Prime Standard Edition 16.1) targeting a Cyclone V FPGA, and generate an IP core FFT (variable streaming, 32K points, 16 bits resolution, natural input order, reversed output order) called fft.
- I create a tcl script called create_library_for_fft.tcl, using as reference the one generated automatically under fft\simulation\mentor\msim_setup.tcl. In this script, I do all the vlog/vcom commands, except the last one regarding fft.vhd, which I do manually in ModelSim (steps 3.2 and 3.5 below).
- In ModelSim
- I create a project.
- I add the fft file fft.vhd and the corresponding testbench fft_tb.vhd (the testbench is minimum to just show the problem).
- I copy the hex files to the same directory and add them to the project.
- I execute the command : source create_library_for_fft.tcl.
- I compile my two files in the project.
- I launch the simulation through Simulate > Start simulation
In my testbench, source_ready = 1, sink_error = 00, sink_valid/sop/eop = 0, inverse = 0, fftpts_in = 2048, sink_real/imag = 0 at the beginning.
Problems observed :
1. When starting the simulation, I see in the command window :
Quote:
# Loading work.auk_dspip_avalon_streaming_block_sink(rtl)
# ** Warning: (vsim-3473) Component instance "sink_FIFO : scfifo" is not bound.
# Time: 0 ps Iteration: 0 Instance: /fft_tb/I_fft/fft_ii_0/auk_dspip_r22sdf_top_inst/sink_ctrl_inst File: ../fft/simulation/submodules/mentor/auk_dspip_avalon_streaming_block_sink.vhd
- "sink_ready" is X all the time except when the reset_n input is asserted to 0.
- "fftpts_out" is XXX... all the time even when the reset_n is asserted to 0.
- I also have "source_sop" = 1 while it should be 0, but maybe it's simply a consequence of the problem, so I didn't focus on this one for the moment.
When looking at the origin of the problem :
- In the top file auk_dspip_r22sdf_top.vhd, the signal "fftpts_out" is UUU..., and :
- "fftpts_out" get its value from "curr_fftpts",
- "curr_fftpts" gets its value from curr_fftpts_s,
- "curr_fftpts_s" is mapped to the output "curr_blk" of the block "auk_dspip_avalon_streaming_block_sink" instantiated as "sink_ctrl_inst",
- In auk_dspip_avalon_streaming_block_sink.vhd :
- "curr_blk" gets its value from "curr_blk_q",
- "curr_blk_q" gets its value from "curr_blk_s",
- "curr_blk_s" gets its value from "sink_fifo_q",
- "sink_fifo_q" is an output of the block "scfifo" instantiated as "sink_FIFO", the block where there is a warning.
Since this block and these files are generated automatically, I never modified them.
I saw in this post that someone had a similar problem where an output of the FFT was always X, and it has been pointed out that it could be due to library files missing, and it was advised to check the msim_setup.tcl file generated automatically. However, all the files mentioned in msim_setup.tcl are also in my tcl file.
Do you have any clue about the origin of the problem ?
I am not familiar with the libraries and tcl files, so maybe this is where I made a mistake.
Thanks in advance.
Jérôme
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Vhdl
I need help with the following task in the VHDL program: Based on the DE2 development board, design a 4-bit Johnson counter. The meter's status is to be displayed on 4 7-segment LED displays (eg 1110). The change in the meter's status is taking place run automatically, e.g. every 1s. Develop a test environment for the designed system.
I need to combine these two codes into one? 4-bit Johnson counter:
I need to combine these two codes into one? 4-bit Johnson counter:
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Ring_counter is
Port( CLOCK: in STD_LOGIC;
RESET: in STD_LOGIC;
Q: out STD_LOGIC_VECTOR( 3 downto 0 ) );
end Ring_counter;
architecture Behavioral of Ring_counter is
signal q_tmp: std_logic_vector( 3 downto 0 ):= "0001";
begin
process( CLOCK, RESET )
begin
if RESET = '1' then
q_tmp <= "0001";
elsif Rising_edge( CLOCK ) then
q_tmp( 1 ) <= q_tmp( 0 );
q_tmp( 2 ) <= q_tmp( 1 );
q_tmp( 3 ) <= q_tmp( 2 );
q_tmp( 0 ) <= q_tmp( 3 );
end if;
end process;
Q <= q_tmp;
end Behavioral;↧
Data Transfer from FPGA-to-HPS
Hi,
I am very new to the Altera FPGA suite (and FPGAs in general), and was looking to get some advice on how to transfer data from the FPGA to the HPS. I've done fair amount of research, but I wasn't sure which method would be the best way to do it. The amount of data will be set to around 37Kilobits. So would the FPGA to HPS bridge be the best? Or limiting the amount of RAM the HPS uses then writing to the other section, then having the HPS read from that memory space? The data would becoming practically continuously. So, I was thinking of a double buffer scenario where the FPGA would write to one buffer, the HPS would read it while the FPGA was writing to the other, then the HPS would read from that one while the FPGA was writing to the other and so on and so forth. I appreciate any advice! I'm using the DE0-Nano-SOC with Cyclone V 5CSEMA4U23C6 Revision C. Thanks!
EDIT: Also I was imagining the FPGA could send an interrupt to the HPS whenever it had finished writing a chunk of data, telling it that its time to read. For the most part I have the HPS side figured out (i'm more of a software guy) Its the FPGA side I'm completely lost.
EDIT2: In terms of speed it only needs to be capable of around 80MBits per second since thats as fast ill be receiving data into the FPGA.
I am very new to the Altera FPGA suite (and FPGAs in general), and was looking to get some advice on how to transfer data from the FPGA to the HPS. I've done fair amount of research, but I wasn't sure which method would be the best way to do it. The amount of data will be set to around 37Kilobits. So would the FPGA to HPS bridge be the best? Or limiting the amount of RAM the HPS uses then writing to the other section, then having the HPS read from that memory space? The data would becoming practically continuously. So, I was thinking of a double buffer scenario where the FPGA would write to one buffer, the HPS would read it while the FPGA was writing to the other, then the HPS would read from that one while the FPGA was writing to the other and so on and so forth. I appreciate any advice! I'm using the DE0-Nano-SOC with Cyclone V 5CSEMA4U23C6 Revision C. Thanks!
EDIT: Also I was imagining the FPGA could send an interrupt to the HPS whenever it had finished writing a chunk of data, telling it that its time to read. For the most part I have the HPS side figured out (i'm more of a software guy) Its the FPGA side I'm completely lost.
EDIT2: In terms of speed it only needs to be capable of around 80MBits per second since thats as fast ill be receiving data into the FPGA.
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