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Data Transfer from FPGA-to-HPS

June 12, 2018, 12:54 pm
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Hi,

I am very new to the Altera FPGA suite (and FPGAs in general), and was looking to get some advice on how to transfer data from the FPGA to the HPS. I've done fair amount of research, but I wasn't sure which method would be the best way to do it. The amount of data will be set to around 37Kilobits. So would the FPGA to HPS bridge be the best? Or limiting the amount of RAM the HPS uses then writing to the other section, then having the HPS read from that memory space? The data would becoming practically continuously. So, I was thinking of a double buffer scenario where the FPGA would write to one buffer, the HPS would read it while the FPGA was writing to the other, then the HPS would read from that one while the FPGA was writing to the other and so on and so forth. I appreciate any advice! I'm using the DE0-Nano-SOC with Cyclone V 5CSEMA4U23C6 Revision C. Thanks!

EDIT: Also I was imagining the FPGA could send an interrupt to the HPS whenever it had finished writing a chunk of data, telling it that its time to read. For the most part I have the HPS side figured out (i'm more of a software guy) Its the FPGA side I'm completely lost.

EDIT2: In terms of speed it only needs to be capable of around 80MBits per second since thats as fast ill be receiving data into the FPGA.
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aocl program fails with error code -2

June 12, 2018, 2:39 pm
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Hi
I am trying to get OpenVino working with Intel FPGA. In one of the steps listed in https://software.intel.com/en-us/art...all-Linux-FPGA. I am supposed to run following command. I have complete Quartus download version 17.1.

aocl program acl0 ~/A10_bitstreams/0-8-1_rc_fp11_16x32_arch17.aocx

I get following error when i do that
aocl program: Running program from /home/iotg-dev70/intelFPGA_pro/17.1/hld/board/a10_ref//linux64/libexec
Programming device: a10gx : Arria 10 Reference Platform (acla10_ref0)
Reprogramming device [0] with handle 1
mmd program_device: Board reprogram failed
OpenCL Notification Callback: Reprogram of device failed
Failed clCreateProgramWithBinary.
Error code: -2
aocl program: Program failed.

Thanks
Yatish
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The data read by io channel cannot be returned to the host

June 12, 2018, 9:01 pm
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Hello：
When I read the data form .v into the kernel using io channel, the data cannot be passed back to the host，but can be calculated in the kernel and written to the external io via the io channel and the result is correct.
Here is our .v file: For simplicity, the avalon-st interface in .v gives a fixed value。

Here is our Qsys:

Here is our kernel:

Here is our host code：
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HPS-to-FPGA DMA Interrupt

June 13, 2018, 12:50 am
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Hi there,

I am working with the Cyclone V and my goal is to transfer Data with the HPS-DMA-Controller (DMA330) and receive an "interrupt" in the FPGA on completion.

The data transfer is already functioning. I configured the DMA-Controller via the DMAengine-API:

Code:
tx = dma_dev->device_prep_dma_memcpy(dma_channel, dma_dst_addr, dma_src_addr, SDMA_BUF_SIZE, DMA_PREP_INTERRUPT );
cookie = dmaengine_submit(tx);
dma_async_issue_pending(dma_channel);

However, I do not receive the interrupt in the FPGA.

I checked the HPS-to-FPGA-interrupt in Qsys. Which gave me 8 Interrupt lines corresponding to 8 DMA-channels in the DMAC.
One thing that is not clear to me, that the DMAengine-API "offers" me 32 DMA channels while there are only 8 "physical" DMA-channels.
How can that be?
Currently I am using the API-channel nr. 7 and expecting the interrupt on the physical channel nr 7.
I did a full recompile including SPL and U-boot with Buildroot.


I would like to narrow this down. I guess either
- there is no interrupt sent ( descriptor/ DMA-Controller not properly configured)
or
- it does not reach the FPGA ( I am missing a step where this HPS-to-FPGA Interrupt connections have to be enabled)
or
- I am listening on the wrong DMA-channel-interrupt

Do you have an Idea what is going wrong here or how to proceed?
Do you know any documentation about the HPS-to-FPGA Interrupts other than the "Cyclone V Hard Processor System
Technical Reference Manual" ?

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CYCLONE10GX SERDES clock

June 13, 2018, 1:40 am
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Hello,
CYCLONE10GX. In one bank I have two groups of LVDS inputs to hard SERDES.
I need to clock inputs to one group directly and the other group with 180 degree phase (inverted) shifted fast clock.
Is there a possibility to choose receiver fast clock inversion in cyclone10gx_io_serdes ?
Thanks
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Include Header not found in the project: Altera-SoCFPGA-HardwareLib-GPIO-CV-GNU

June 13, 2018, 3:04 am
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Hello,
I downloaded this example : Altera-SoCFPGA-HardwareLib-GPIO-CV-GNU.
When I build the project the compiler cannot find the following headers:
#include "alt_generalpurpose_io.h"
#include "alt_interrupt.h"
#include "alt_globaltmr.h"
#include "alt_clock_manager.h"

Can I download these files?
What path is it necessary to indicate in the project?
Thanks for your help
Jerome
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[Cyclone V PCIe Hard IP]: Avalon to PCIe read issue

June 13, 2018, 3:48 am
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Dear all,


We are using Cyclone V PCIe Hard IP core with Quartus 16.1. We are using Requester/Completor mode so that we can perform PCIe read and write operations from Avalon master. In our design, we are using DMA controller which is connected to Txs component of PCIe and with onchip memory. And here is the problem and our observations so far.

  1. When we configure DMA to transfer data from offchip meory (via Txs of PCIe) to onchip memory, after some time strange issue happens. Txs slave accepts read requests generated by Avalon master (DMA) by de-asserting wait_request but does not generate read_data_valid. And hence our DMA hangs.
    1. Note that if I configure DMA to transfer only 4 bytes each time, it works well each time. But if I set DMA length to 8,16,32 or 64, it hangs.

  2. We are not facing issue with PCIe write. I mean if I configure DMA to read data from onchip memory and transfer it to offchip memory via Txs of PCIe, it works each time.
  3. We have checked this with Intel (Altera's) 32 bit DMA controller and with our own DMA controller.


If anybody could point us where we should be looking for to identify the root cause for this, we would appreciate.

Thank you,
Bhaumik
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Can't create new service request

June 13, 2018, 5:54 am
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I can't create new service request.
I fill the form out.
Hit continue request and I get web search results.
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Need some help

June 13, 2018, 5:58 am
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Hey could someone help me and fix the problem , i can't find where i made the mistake , i'm new to this...

library ieee;
use ieee.std_logic_1164.all;





entity sck is
port (

i_bit0 : in std_logic_vector(1 downto 0);
o_bit1 : in std_logic_vector(1 downto 0);
o_bit2 : out std_logic_vector(5 downto 0));
);


end sck;

architecture behavioral of sck is
signal A: std_logic_vector(5 downto 0);
begin
A<= o_bit1 and o_bit2;
process (A)
begin
case i_bit0
when "00" => A <="011100";
when "01" => A <="101010";
when "10" => A <="110011";
when "11" => A <="111111";
when others => null;
end case;
end process;

end behavioral;
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Arria 10 LW Bridge and LCD 16207

June 13, 2018, 8:48 am
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Hi,
I am using an Arria 10 with Linux as the OS.

I connected the LCD16207 in QSYS to the lightweight bridge on the Arria 10 HPS. I am able to display strings from a test program, but when I try to implement the functions from the test program into my main program, it does not seem to write properly. My main program is threaded and has access to the LW bridge from each thread. What I found was that if another process accesses the LW bridge, it seems to prevent the LCD screen data from being displayed. Here comes the interesting part, on an oscilloscope, I probed the LCD pins and found that when the LW bridge is accessed (both read and write), there is a pulse on the Enable line of the LCD. This occurs even if the LCD memory mapped register is not being accessed. I think this is preventing the LCD from displaying the string properly.

As a note, I am using /dev/mem and mmap to access the lw bridge. I have not had a problem before with the lw bridge and controlling other IP such as the address extender and Altera Serial Flash Controller II.

Why does the enable line have a signal when I am not writing to the LCD 16207? Is there something I am missing here or should the writes to other memory mapped bridge locations not affect the LCD 16207 core?

Thank you
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[Arria 10 GX Development Kit] PCIe for External Memory BAR4 length

June 13, 2018, 10:24 am
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Hello everyone,

I've been developing a PCIe-based co-processor system using Arria 10 GX Dev Kit and I am having some trouble configuring a proper BAR4 size to address all slaves connected to the PCIe DMA IP. For data transfers from the host to the FPGA, I am using the a Linux DMA driver adapted from the altera_dma driver provided along with the reference design (PCI Express Avalon-MM DMA Reference Design).

My system interconnection is as follows:

EP IP START - END ADDR
PCIe Hard IP (DUT)
|
|
|--------------------------------- EMIF(ctrl_avmm_0) 0x0000_0000 - 0x0FFF_FFFF (256 MB) (28bits)
|--------------------------------- ONCHIP_MEM 0x5000_0000 - 0x0000_001FF (512 B) (9 bits)
|--------------------------------- CO-PRO 0x1000_0000 - 0x0000_003FF (1024 B) (10bits)

TOTAL ADDRESSES EXPECTED: 0x1000_0000 + 0x0200 + 0x0400 = 0x10000600

For this configuration, Qsys calculates a 31bit size for BAR4 (0x4000_0000), configure as a 64bit non-prefetchable memory. This length should be enough to cover all EMIF addresses, plus the CO-PRO and ONCHIP. Therefore, from my DMA driver I should be able to read or write single words (iowrite32, ioread32) to any offset from the BAR4 start address, right?

For example, if I wanted to write a 32bit word to the first position on the ONCHIP memory I should:

int onchip_base = 0x50000000;
int data = 0xAB;
__iomem * ptr = pci_ioremap_bar (pdev, 4);
iowrite32(data, ptr + onchip_base);
...

However, using this strategy I am able to write or read positions on EMIF and CO-PRO (addresses smaller than 0x40000000), but not on the ONCHIP_MEM. I believe the problem is because the base address for the ONCHIP_MEM (0x5000_0000) is greater than the calculated size of the BAR4 (0x40000000). This parameter is not configurable from the the Qsys GUI interface. The reference design documentation says it is automatically calculated when I finish the interconnection.

I would like to know if any of you guys have had this problem and what I am doing wrong. I want to be able to write any position on the design using iowrite32 calls.

Thank you a lot for any help you could give me.

Amorim
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FPGA-to-HPS Bridges Design Example

June 13, 2018, 10:40 am
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Hi Everyone,

I'm working to develop an FPGA-HPS design which allows the FPGA to write to the HPS DDR3 and then have the HPS read from that memory space. So far this is the only example I've found for this type of design: https://www.altera.com/support/suppo...n-example.html I was able to modify the Quartus project for my DE0-Nano-SoC Cyclone V board, but when trying to compile the baremetal application in DS5 EDS Eclipse I ran into this error: (Path)/Altera-SoCFPGA-HardwareLib-FPGA2HPS-Bridge-CV-GNU/alt_bridge_manager.c:93: undefined reference to `memcpy_s'. Now all the files including this alt_bridge_manager.c came directly from the Altera design example. So far I've tried changing the std in the makefile from C99 to C11, no luck. Also, I found a post stating that if you put:
Code:
#define __STDC_WANT_LIB_EXT1__ 1
Then it would fix the error, however that did not work either, and I found that when running build in the DS5-Workspace in eclipse it actually stripped that line out of the file. I'm pretty lost here and would appreciate any help on the project for additional info:

Board: DE0-NANO-SoC Cyclone V 5CSEMA4U23C6
OS: Windows 10
IDE: Eclipse DS5 Workspace started from SoC EDS Terminal
Project: https://www.altera.com/support/suppo...n-example.html

EDIT: Ran the make from the SoC EDS, no longer strips out that #define statement like the DS5 Eclipse does, but still throws the error
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License problem after reinstalled the software DS-5 AE

June 13, 2018, 11:20 am
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Hello,
I uninstalled the DS-5 software and the I installed the new version.
My License Activation Code is: P34E2-07160-3E377 (November 2017)
My Product is: ESW-SOCEDS-DS5-FIX
It seems to find my license but when I compile the first example I got a license error.

I tried to install again my license but it fail. I cannot find my serial number. I cannot get the license.
What can I do?
Thanks for your help
Jerome
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Quartus II Fitter error in connecting the output of IOPLL to refclk of ATX PLL

June 13, 2018, 12:20 pm
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Hello,

I am creating a Quartus project to transmit high-speed data using the Arria 10 Transceiver Native PHY. I am supplying the the serial clock (at 1.5GHz) to the tx_serial_clk0 using Arria 10 Transceiver ATX PLL which generates 1.5GHz clock using input 150MHz clock. I am creating this 150Mhz clock using another PLL (Altera IOPLL) that takes the 50MHz FPGA clock as the input. I have attached the qsys design screenshot of the project.

The compilation of the design is successful. However, the fitter prompts an error which I am not able to understand. The error prompt is:

Error (11192): Input port "REF_IQCLK[0]" of "HSSI_PMA_LC_REFCLK_SELECT_MUX" cannot connect to PLD port "OUTCLK[0]" of "IOPLL" for atom "tx_phy_qsys:tx_phy_qsys_1|tx_phy_qsys_altera_iopl l_171_zoxksfy:iopll_0|altera_iopll:altera_iopll_i| twentynm_iopll_ip:twentynm_pll|iopll_inst".
Extra Info (13133): Output port's "OUTCLK[0]" atom name is "tx_phy_qsys:tx_phy_qsys_1|tx_phy_qsys_altera_iopl l_171_zoxksfy:iopll_0|altera_iopll:altera_iopll_i| twentynm_iopll_ip:twentynm_pll|iopll_inst".
Extra Info (13134): Input port's "REF_IQCLK[0]" atom name is "tx_phy_qsys:tx_phy_qsys_1|tx_phy_qsys_altera_xcvr _atx_pll_a10_171_7s4kdty:xcvr_atx_pll_a10_0|a10_xc vr_atx_pll:a10_xcvr_atx_pll_inst|twentynm_hssi_pma _lc_refclk_select_mux_inst".
Extra Info (12879): Input port "REF_IQCLK[0]" of "HSSI_PMA_LC_REFCLK_SELECT_MUX" can connect to:
Extra Info (12880): Port "O_REFCLK_A[0]" of "HSSI_REFCLK_DIVIDER"


It basically says that I cannot provide the output of the IOPLL to the pll_refclk0 of the ATX PLL. But, the ATX PLL needs reference clock of 150MHz. It does not make sense to me. Please help.

Thank you
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Verilog Coding

June 13, 2018, 12:53 pm
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Hello,

I'm getting the following error when I'm implementing the below Verilog code.

[Synth 8-403] loop limit (65536) exceeded

parameter N=10;
parameter M=8;
parameter depth=(1<<N);


reg [M-1:0]stack_mem[depth-1:0];


always@(posedge clk)
begin
if (rst==1'b1)
begin
next_sp=0;
dataout=0;
for(i=0;i<(depth-1);i=i+1)
begin
stack_mem[i]=0;
end
end
end


Here "For loop" has to increase only up to 1023 but again why I'm getting loop limit exceeded error?

Can anyone help me out?

Thanks in advance.
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Source Synchronous Interface Input and Output Delays

June 13, 2018, 2:26 pm
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Hi Everyone,

This is my first post and I tried looking for a solution before asking it here. I am new to static timing and have been studying source synchronous interfaces and how to constrain them. In some examples here within Altera Resources itself, they use a virtual clock to set the output delays. In some examples, a generated clock which is defined at the output port of the design is used to set the output delays.

So, is there no difference between using a virtual clock and a output clock for setting output delays?

Of course The same question about the input delays on the input ports, whether we should use the virtual clock or the clock defined on one of the input ports. Does it matter? If not, why?

Please let me know if my question is unclear.
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Duplicate GPIO pins in Pin Planner

June 12, 2018, 7:15 am
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In the Pin Planner, I want to switch physical locations of my pin names. However, everything is in duplicate. I saw a publication of this issue in Quartus II and and read that this issue would not happen in the next version. Here I am in Quartus Prime and it is still happening. Do I just reassign each pair? Please advise.
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Fpga alarm clock (urgent help)!

June 12, 2018, 7:59 am
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Hello everyone. I have Xilinx BASYS 3 FPGA BOARD. My homework was about alarm clock. I found the code on http://www.fpga4student.com/2016/11/...k-on-fpga.html and I arranged the switches accordingly but I cannot do what I want on LEDs. What should be done to finish it? If you help me I will be very appreciated and I have only 6 hours submit it and pass the course.

Thanks in advance
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FFT IP simulation : Warning: "sink_FIFO : scfifo" is not bound

June 12, 2018, 10:49 am
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Hello,

I am trying to simulate the Intel FFT IP in ModelSim Intel FPGA Starter Edition 10.5b, and I encounter a problem : the output "sink_ready" is X as soon as the reset is deasserted, and the fftpts_out is XXX... all the time.

Next, I explain first what I did, then I explain the problems observed. I put in attachment a screenshot of the simulation to show the problems described, the tcl files, and the entire folder with the quartus project and the ModelSim simulation under fft_example_tb.

Steps :
  1. I create a Quartus project (Prime Standard Edition 16.1) targeting a Cyclone V FPGA, and generate an IP core FFT (variable streaming, 32K points, 16 bits resolution, natural input order, reversed output order) called fft.
  2. I create a tcl script called create_library_for_fft.tcl, using as reference the one generated automatically under fft\simulation\mentor\msim_setup.tcl. In this script, I do all the vlog/vcom commands, except the last one regarding fft.vhd, which I do manually in ModelSim (steps 3.2 and 3.5 below).
  3. In ModelSim
    1. I create a project.
    2. I add the fft file fft.vhd and the corresponding testbench fft_tb.vhd (the testbench is minimum to just show the problem).
    3. I copy the hex files to the same directory and add them to the project.
    4. I execute the command : source create_library_for_fft.tcl.
    5. I compile my two files in the project.
    6. I launch the simulation through Simulate > Start simulation



In my testbench, source_ready = 1, sink_error = 00, sink_valid/sop/eop = 0, inverse = 0, fftpts_in = 2048, sink_real/imag = 0 at the beginning.

Problems observed :
1. When starting the simulation, I see in the command window :
Quote:
# Loading work.auk_dspip_avalon_streaming_block_sink(rtl)
# ** Warning: (vsim-3473) Component instance "sink_FIFO : scfifo" is not bound.
# Time: 0 ps Iteration: 0 Instance: /fft_tb/I_fft/fft_ii_0/auk_dspip_r22sdf_top_inst/sink_ctrl_inst File: ../fft/simulation/submodules/mentor/auk_dspip_avalon_streaming_block_sink.vhd
2. As said at the beginning, I have a problem with the following outputs :
  • "sink_ready" is X all the time except when the reset_n input is asserted to 0.
  • "fftpts_out" is XXX... all the time even when the reset_n is asserted to 0.
  • I also have "source_sop" = 1 while it should be 0, but maybe it's simply a consequence of the problem, so I didn't focus on this one for the moment.


When looking at the origin of the problem :
  • In the top file auk_dspip_r22sdf_top.vhd, the signal "fftpts_out" is UUU..., and :
    • "fftpts_out" get its value from "curr_fftpts",
    • "curr_fftpts" gets its value from curr_fftpts_s,
    • "curr_fftpts_s" is mapped to the output "curr_blk" of the block "auk_dspip_avalon_streaming_block_sink" instantiated as "sink_ctrl_inst",

  • In auk_dspip_avalon_streaming_block_sink.vhd :
    • "curr_blk" gets its value from "curr_blk_q",
    • "curr_blk_q" gets its value from "curr_blk_s",
    • "curr_blk_s" gets its value from "sink_fifo_q",
    • "sink_fifo_q" is an output of the block "scfifo" instantiated as "sink_FIFO", the block where there is a warning.



Since this block and these files are generated automatically, I never modified them.

I saw in this post that someone had a similar problem where an output of the FFT was always X, and it has been pointed out that it could be due to library files missing, and it was advised to check the msim_setup.tcl file generated automatically. However, all the files mentioned in msim_setup.tcl are also in my tcl file.

Do you have any clue about the origin of the problem ?
I am not familiar with the libraries and tcl files, so maybe this is where I made a mistake.

Thanks in advance.
Jérôme
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Vhdl

June 12, 2018, 11:31 am
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I need help with the following task in the VHDL program: Based on the DE2 development board, design a 4-bit Johnson counter. The meter's status is to be displayed on 4 7-segment LED displays (eg 1110). The change in the meter's status is taking place run automatically, e.g. every 1s. Develop a test environment for the designed system.

I need to combine these two codes into one? 4-bit Johnson counter:
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Ring_counter is
Port( CLOCK: in STD_LOGIC;
RESET: in STD_LOGIC;
Q: out STD_LOGIC_VECTOR( 3 downto 0 ) );
end Ring_counter;

architecture Behavioral of Ring_counter is
signal q_tmp: std_logic_vector( 3 downto 0 ):= "0001";
begin
process( CLOCK, RESET )
begin
if RESET = '1' then
q_tmp <= "0001";
elsif Rising_edge( CLOCK ) then
    q_tmp( 1 ) <= q_tmp( 0 );

q_tmp( 2 ) <= q_tmp( 1 );
q_tmp( 3 ) <= q_tmp( 2 );
q_tmp( 0 ) <= q_tmp( 3 );
end if;
end process;
Q <= q_tmp;
end Behavioral;
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