Quantcast
Channel: Altera Forums
Viewing all 19390 articles
Browse latest View live
↧

Can't generate gmon.out with gprof

June 28, 2018, 10:35 am
$
0
0
Hi all,

I'm trying to run GPROF on my project (Quartus Prime 18.0).
I have added the "enable_gprof" and "enable_exit" flags in the BSP, and I can see it does pass the -pg option when building.
I have -g and -O0 as well.
The application runs but I cannot get any gmon.out file output.

What am I missing? I have been stuck with this for hours and can't seem to figure it out...
↧
Search

MAX 10 Internal Oscillator

June 28, 2018, 10:38 am
$
0
0
I am using a 10M2SCU169C8G demo board from QM Tech. Created an IP variation of the Internal oscillator which is supposed to output 116 Mhz. When I check the frequency, it is generating a frequency 74 Mhz
instead. Can anyone tell me why this could be happening? There are only two outputs variation of the clock available. One is 55 Mhz and the other is 116 Mhz but, that is not what it's beinggenerated.
↧
↧

I Have imported the correct libraries and still get an error.

June 28, 2018, 11:30 am
$
0
0
So i have this little piece of a datapath entity.

library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity Datapath is port (
R1, R2, E1, E2, E3, E4, E5: in std_logic;
CLOCK_50: in std_logic;
SEQIN,SQR: in std_logic_vector (9 downto 0);
SW_erro, end_game, end_time, end_round: out std_logic;
Smt: out std_logic_vector(3 downto 0);
SmN: out std_logic_vector (3 downto 0);
result: out std_logic_vector (7 downto 0)
);

end Datapath;

architecture arqdtp of Datapath is
signal SmSwitches: std_logic_vector(2 downto 0);
signal SeqRom, SeqSw: std_logic_vector(9 downto 0);
signal SmT_in, SmN_in: std_logic_vector(3 downto 0);
signal C: std_logic;
begin
-- Registrador e Somador:
P1: process(CLOCK_50,R1)
begin
if (R1 = '1') then -- R1 Time reset
Smt_in<= "0101";
elsif (CLOCK_50'event AND CLOCK_50 = '1') then
if (E1 = '1') then
Smt_in <= Smt_in - '1';
SmT <= SmT_in;
end if;
end if;
end process;

P2: process(CLOCK_50,R2)
begin
if (R2 = '1') then -- R2 reset Next round
SmN_in<= "0000"; -- Soma Next round
elsif (CLOCK_50'event AND CLOCK_50 = '1') then
if (E3 = '1') then
SmN_in <= SmN_in + '1';
SmN <= SmN_in;
end if;
end if;
end process;

-- Comparador:
end_time <= '1' when (Smt_in = "0000") else '0';
end_round <= '1' when (SmN_in = "1010") else '0';
end_game <= '1' when (SeqSw = SeqRom)else '0';
SmSwitches <= (SEQIN(1)+SEQIN(2)+SEQIN(3)+SEQIN(4)+SEQIN(5)+SEQI N(6)+SEQIN(7)+SEQIN(8)+SEQIN(9)); -- For some reason it gives me the error here.
SW_erro<= '1' when (SmSwitches > "0100") else '0';

-- Sequencia secreta
P3: process(CLOCK_50,E4)
begin
if (E4 = '1') then -- Sequencia do Jogo reset
SeqSw<= "0000000000"; -- Sequencia 4 bits
elsif (CLOCK_50'event AND CLOCK_50 = '1' and E2 = '1') then
SeqRom <= SEQR;
end if;
end process;

-- Sequencia escolhida
P4: process(E5)
begin
if (E5 = '1') then -- Sequencia Escolhida reset
SeqRom<= "0000000000"; -- Sequencia 10 bits
C <= end_game;
result <= ("16" * C) + ("10" - SmN);
end if;
end process;
end arqdtp;

and i am still getting: Error (10327): VHDL error at Datapath.vhd(53): can't determine definition of operator ""+"" -- found 0 possible definitions
Can anyone please help me? It is urgent.
↧

Intel HLS Compiler Waveform Simulation terminating

June 28, 2018, 4:24 pm
$
0
0
Hi,

I am working with Quartus 17.1 and I have compiled a project using HLS. I am able to generate the project directory and the associated verilog files. I have used the -ghdl flag while using i++ to compile for the Arria10 FPGA platform. The vsim.wlf is generated in the <project_dir>/verification folder and I am able to open that on Modelsim as well. However, when I run the project executable, I receive the message "The simulation process encountered an error and has been terminated."

This is the error generated by the transcript.log file of Modelsim. This is attached as intel_hls_simulation_error.png below.

Curious, I went ahead to look at the specified line in the transcript. That is attached as break_in_module.png below. I am not able to make sense of this error. I tried to run the the given example files as well, however, I faced the same issue. The simulation got terminated that time as well. Therefore, I do not believe it is my HLS code which is breaking the simulation.

I do not understand the reason for this. Please provide inputs or fixes, if any. Thank you!

NOTE: I am working with Centos 6.8 and have the necessary packages installed. I used to use Centos 7.4 but had to revert to 6.8 upon finding out that arbitrary datatypes were not being supported in Centos 7.4.
Attached Images
↧

How to reduce Interconnect Delay?!

June 28, 2018, 11:35 pm
$
0
0
Hi,
I have designed a mux in Cyclone IV-E device.
I need to meet the Pin to Pin delay constraint of 10 ns.
Tools used are Quartus II 14.0 and Timequest.

I am geting data path with delay of 13.309ns...IC delay of this path is found to be ~7.5ns:(:confused:
Part of report is added below.
Slack From Node To Node Launch Clock Latch Clock Relationship Clock Skew Data Delay
-3.309 unc_jtag_tdi tdi_unc2 n/a n/a 10 0 13.309



Is it possible to reduce this delay?

The logic implemented is a combo mux!
I have even tried a direct pin to pin mapping wihout any logic...and data delay is 7.496 for that(IC Delay is 3.640ns)!!


Thanks,
Neeraj G N
↧
↧

Stratix V GX dev kit does not work

June 29, 2018, 1:47 am
$
0
0
Hi,

After i flashed my device. No LED on the board is turned on and the fan runs will full speed. Is the board damaged?
thanx
↧

The modular SGDMA dispatcher module device driver files

June 29, 2018, 3:27 am
$
0
0
Hii

im using MSGDMA core to transfert data between FPGA and HPS-DDR3 on DE1-SOC board , i create my system using the Qsys but it still need the software which will activate the MSGDMA to start transfert. i read in this document "Modular SGDMA Dispatcher Core"about device driver files.
the documment tells that The modular SGDMA dispatcher module provides the following device driver files

where i will found this drivers ?
Attached Images
↧

DEFAULT IO LEVEL during Configuration

June 29, 2018, 6:05 am
$
0
0
Hi,

Can we set some selected FPGA pins default value to some defined state(1,0 or high impedance) during configuration cycle?

Regards,
Sanju
↧
Search

HPS EMAC DMA engine always in reset...

June 29, 2018, 8:19 am
$
0
0
Hello everyone !

In my current baremetal project, I use a Cyclone V 5CSXFC6C6 and I want to use the HPS emac in RGMII.
On the board I developped, i had to use the FPGA I/O to route the GMII signals of the HPS.

My QSYS project is based on this project (for the emac management) : https://rocketboards.org/foswiki/Pro...IExampleDesign
So I use QSYS "Emac interface splitter" & "gmii to rgmii adapter" module to make the GMII to RGMII conversion.
The PHY i use is the Mikrel KSZ9021RL.

To initialize HPS Emac & PHY, I use the method described in Cyclone V Hard Processor System Technical Reference Manual (cv_5v4.pdf), Ethernet Media Access Controller / Ethernet MAC Programming model.

The "EMAC FPGA interface initialization" seems to works fine in my HPS software :
  • I reset the PHY
  • I reset the HPS EMAC0
  • I configure the EMAC0_clk to 250MHz
  • I bring the PHY out of reset and I check if rx_clk is present (it is the case)
  • The Qsys "gmii-2-rgmii" adaptor that I developped is running, so I assume that the corresponding clocks are correctly propagating.
  • I set the EMAC0 to GMII mode
  • I start the Ethernet Controller FPGA interface
  • I bring the EMAC out of reset


Then, on my hardware, I have checked that both rx_clk (from PHY) and tx_clk (from EMAC) are present and are 125MHz (and they are).

According to cv_5v4.pdf, I now have to reset the EMAC0 DMA module and continue the init but my problem appears here:
For the DMA initialization, I have to reset the EMAC DMA module (Bus Mode Register, bit 0) and wait for the reset completion by pooling the same bit.
--> The issue is that the module never goes back from reset...

According to the documentation :
"The reset operation is completed only when all resets in all active clock domains are de-asserted. Therefore, it is essential that all the PHY inputs clocks (applicable for
the selected PHY interface) are present for the software reset completion."

I'm quite sure that my PHY rx_clk is present at the emac0_rx_clk_in and that emac0_clk is successfuly set to 250MHz.

Does someone have any idea of what happens here ? I think about it for some days, and I must admit that I have no more ideas...

Thank you !

PS : on a previous board, I used the same HPS code to manage the EMAC and it worked great ! The only difference is that the PHY was connected to the HPS EMAC pins and not like here to FPGA pins...
↧
↧

VHDL Port Mismatch Error

June 29, 2018, 8:54 am
$
0
0
Hi Everyone,

I have defined a component in my VHDL Flash file as shown in the Capture 1 attachment.

And I have generated a Flash IP.
The Flash is instantiated as shown in Capture 2.

When I compile the code, it throws in an error saying:

Error (12012): Port direction mismatch for entity "Flash_intf:Flash_Interface_Program|Flash:Flash_in st" at port "flash_nwe". Upper entity is expecting "Input" pin while lower entity is using "Output" pin.

Can anyone please tell me why am I getting this port mismatch error?

Thank you
Attached Images
↧

DQS Input and Output Timing Constraints

June 29, 2018, 2:59 pm
$
0
0
Greetings,

I have a DDR controller which has a bidirectional DQS (data strobe) signal. In read states, the DDR device is driving DQS, as well as some data bits which have timing relationship to the input DQS. In write states, the FPGA drives DQS as well as
some data bits which have a different timing relationship to the output DQS.

During writes, I have the data bits being clocked out with a 0-degree clock, and the DQS line is being clocked out with a 90-degree version of the same clock. This helps center the data eye around the outgoing DQS clock.

Here's what I've tried:

Code:
#Input Constraints
create_clock -name CLK_ddr_ldqs_INPUT -period $DDR_CLK_PERIOD [get_ports ddr_ldqs_n]
create_clock -name virt_clk -period $DDR_CLK_PERIOD
set_multicycle_path 0 -from virt_clk -to CLK_ddr_ldqs_INPUT
set_input_delay -clock virt_clk $tDQSQ -max [get_ports $input_ports]
set_input_delay -clock virt_clk -$tQHmin -min [get_ports $input_ports]
set_input_delay -clock virt_clk $tDQSQ -max [get_ports $input_ports] -clock_fall -add_delay
set_input_delay -clock virt_clk -$tQHmin -min [get_ports $input_ports] -clock_fall -add_delay


#Output Constraints
set CLK_ddr_ldqs_n_OUTL CLK_ddr_ldqs_INPUT;
set_output_delay -clock $CLK_ddr_ldqs_n_OUTL $tDS -max [get_ports $input_ports]
set_output_delay -clock $CLK_ddr_ldqs_n_OUTL -$tDH -min [get_ports $input_ports]
set_output_delay -clock $CLK_ddr_ldqs_n_OUTL $tDS -max [get_ports $input_ports] -clock_fall -add_delay
set_output_delay -clock $CLK_ddr_ldqs_n_OUTL -$tDH -min [get_ports $input_ports] -clock_fall -add_delay
The problem is, when I look at the timing path in TimeQuest, I see the output path:

From Node: inst5|altpll_component|auto_generated|pll1|clk[0]
To Node: ddr_dq[12]
Launch Clock: inst5|altpll_component|auto_generated|pll1|clk[0]
Latch Clock: CLK_ddr_udqs_INPUT

(clk[0] is the 0-degree clock)

but in the "Waveform" viewer, it is showing that the Launch clock and Latch clock are the same (there is no 90-degree phase shift).

i tried replacing
Code:
set CLK_ddr_ldqs_n_OUTL CLK_ddr_ldqs_INPUT;
with :
Code:
create_generated_clock -name CLK_ddr_ldqs_n_OUTL -source { inst5|altpll_component|auto_generated|pll1|clk[3] } [get_ports ddr_ldqs_n]
(clk[3] is the 90-degree clock)

But I get the warning:
Code:
Warning (332049): Ignored create_generated_clock at DDRCtrlTimingConstraints.sdc(327): Incorrect assignment for clock.  Source node: ddr_ldqs_n already has a clock(s) assigned to it.  Use the -add option to assign multiple clocks to this node.  Clock was not created or updated.
which ultimately leads to an error
Code:
Error (332000): can't read "CLK_ddr_ldqs_n_OUTL": no such variable
.

I tried doing what it said and adding the "-add" flag. While this does get rid of the warning, it still doesn't get rid of the error.

What's the right move here?
↧

BSP design and question about EMIF IP

June 30, 2018, 4:13 am
$
0
0
Hi, I am new to design FPGA.

I have a PAC board with it's BSP.
However, I still want to customize my own BSP.
I follow the tutorial about how to make customized BSP.

Code:
Here is my step:
Have a copied of a10_ref BSP.
Modified device.tcl device to 10AX115N3F40E2SG. (refer to PAC device.tcl)
In board.qsys, acl_ddr4_a10.qsys, acl_ddr4_a10_core.qsys, Sync All System Infos -> Generate HDL -> Finish
Modified pin assignment. (refer to PAC pin assignment, like PCIE, memory, refclk ...)
In acl_ddr4_a10_core.qsys
          ddr4a EMIF IP
                  General
                            set memory clock frequency to 1066. ( I set to this because my board memory is DDR4 2133, and a10_ref use DDR4 2400)
                            use recommanded PLL reference clock frequency
                  Mem Timing
                            set Speed bin to -2133
          Sync All System Infos -> Generate HDL -> Finish
In board.qsys
          kernel_clk_gen
                  set REF_CLK_RATE to 100
          config_clk
                  set Explicit clock rate to 100000000
          Sync All System Infos -> Generate HDL -> Finish
In top.v
          reg config_clk; // because in a10_ref, it need 50MHz config_clk, and I only have 100MHz kernel_pll_refclk
          always@(posedge kernel_pll_refclk or negedge perstl0_n) begin
            if (!perstl0_n)
              config_clk <= 0;
            else
              config_clk <= ~config_clk;
          end
However, the system will crash when I try to send data to external memory DDR4. I have upload the log file.
It would be very helpful, if someone can tell me what's wrong.

and I also have some question about EMIF IP.
what should I set in General memory clock frequency?
what should I set in General PLL reference clock frequency?
what is Speed bin in Mem Timing?
I know I have to assign a pin to pll_ref_clk, is this pin clock should match PLL reference clock frequency?

and in a10_ref emif ip, it set memory clock frequency to 1200, and PLL reference clock frequency to 300MHz,
I am not sure what clock it provide to pll_ref_clk, but in top.sdc file I see an assignment "create_clock -period 150MHz [get_ports pll_ref_clk]"
So I guess it assign 150MHz clock when it set PLL reference clock frequency to 300MHz. Why it work?
Attached Files
↧

Problem with Quartus and PIN plan (EP4CE6)

June 30, 2018, 7:01 pm
$
0
0
I am currently working with FPGA as part of a course at the university. At the university we use Terasic Altera Cyclone III EP3C16 Development & Education boards, I am quite familiar with it, I can find it in Quartus, have user manual with all of the pins and everything works fine...

However, I recently bought an FPGA from Aliexpress in order to exercise at home. I am not completely sure which model it is but it should be hynix EP4CE6 with Cyclone IV EP4CE6E22C8N. I have two problems with it:

1. I cannot find the following chip in Quartus (there is only Cyclone IV EP4CE6E22C8, but not Cyclone IV EP4CE6E22C8N)
2. I cannot find the user manual with all of the pins for LEDs, switches, BTNs, 7SegDisplays...

Here is how the board and chips look like:

↧
↧

Input signal pin as global clock

July 1, 2018, 3:09 am
$
0
0
I have a Wavesshare EP4CE10 development board and want to input a 10MHz clock to go in as a global clock.


Unfortunately, the dev board seems to have only one clock input physically accessible on the pcb (BGA device).


I would like to try use one of the normal IO pins and internally steer this input to one of the internal global clock signals. Assignment Editor (assignment name) setting the input pin to "global" gives me an error.

Any way to do this?


Could try generating some internal logic eg a mux. But don't know how to set this internal node as global clock.

PS using VHDL
Also compilation reports shows the signal, not as "global" but as "non-global high fan out" so its seems it is not being automatically assigned as global!
↧

How to build object libraries and assembly Macro-Instructions libraries?

July 1, 2018, 2:14 pm
$
0
0
For bare-metal application I need to build libraries of object files and libraries of assembly macro-instruction.
I look for information in documentations but I could not find anything.
Thanks for your help.
Kind regards
Jerome
↧
Search

Impossible to modify the size of an expression in the DS-5 AE Debbuger

July 1, 2018, 2:19 pm
$
0
0
Hello,
I would like to show in the expression tab a word in memory (4bytes).
The address of the word is made from a label + an offset.
When I show it in the expression tab I can only see one byte. (See attached file)
What can I do to specify the size of the data?
Thanks for your help.
Jerome
Attached Images
↧

AM transmitter behaves weird (Cyclone II)

June 28, 2018, 9:53 am
$
0
0
Hello. I tried to make AM transmitter and I got petty wird behavior. This code, which I post here was the only one I got working. Problems start appearing when I change div2(17) or div2(13) to any other numbers than 17 or 13. There should be transmited two frequencies which change once about one second, but when the numbers got changed one of frequencies got noisy or completly disapear, sometime disaper both or there is only the 6,5MHz frequency. I used LEDs insead of antena for easier debugging. What am I doing wrong and can do to make behavior correct. Thank you very much.

Code:
library IEEE;use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;




entity testovaci is
    Port (
        clk :  in std_logic;
        LED :  out std_logic_vector(2 downto 0)                 
);
end testovaci;


architecture Behavioral of testovaci is
    signal div : std_logic_vector(2 downto 0);
    signal div2: std_logic_vector(20 downto 0);
    signal div3: std_logic_vector(26 downto 0);
    signal  count :  std_logic_vector(2 downto 0);
begin


process (clk)
begin
    if clk='1' then
        div<=div+1;
        div3<=div3+1;
    end if;
    if div="000" and clk='1' then
        div2<=div2+1;
    end if;
    if div(2)='1' then
            if div3(24)='0' then
                if div2(17)='1' then
                    count <= "111";
                else
                    count <= "000";
                end if;
            else
                if div2(13)='1' then
                    count <= "111";
                else
                    count <= "000";
                end if;
            end if;
    else
        count <= "000";
    end if;
end process;


LED(2 downto 0) <=  count(2 downto 0);


end Behavioral;
↧
↧

modelsim erro Unresolved defparam reference to 'dcfifo_component'

June 28, 2018, 10:18 am
$
0
0
Hi,

I'm back with FPGAs and I'm trying to simulate a simple FIFO from the standard IP catalogue for an Arria 10: 10AX115S3F45E2SG.
Because my job is a little part of a big project I have write down a code without pins specification, because for now I only want RTL simulation.

I have tested the test bench with my logic and it works, I can simulate it with modelsim but when I put the FIFO Modelsim complains, I attach the transcript at the end of the post.
I checked all the files that modelsim complains and are all there in the folder specified.

for information my configuration is:
Ubutnu-Mate 16.04
Quartus Prime 18.0 (with license)
Modelsim INTEL FPGA STARTER EDITION 10.5b

thanks for the help,
Guillermo

Code:
#  vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L  twentynm_ver -L twentynm_hssi_ver -L twentynm_hip_ver -L twentynm -L  twentynm_hssi -L twentynm_hip -L rtl_work -L work -L  inputBuff2Clks_fifo_180 -voptargs="+acc"  Compactor_tb
# vsim -t 1ps  -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L twentynm_ver  -L twentynm_hssi_ver -L twentynm_hip_ver -L twentynm -L twentynm_hssi -L  twentynm_hip -L rtl_work -L work -L inputBuff2Clks_fifo_180  -voptargs=""+acc"" Compactor_tb
# Start time: 19:02:24 on Jun 28,2018
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_textio(body)
# Loading work.compactor_tb(beha)
# Loading work.ut_compactor(beh)
# Loading work.ut_compactor_basic(beh)
# Loading ieee.numeric_std(body)
# Loading verilog.vl_types(body)
# Loading work.inputbuff2clks(rtl)
# Loading inputBuff2Clks_fifo_180.inputBuff2Clks_fifo_180_czaw2fq
#  ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(69):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.enable_ecc.
#    Time: 0 ps  Iteration: 0  Instance:  /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0 File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v
#  ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(70):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.intended_device_family.
#    Time: 0 ps  Iteration:  0  Instance: /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0  File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v
#  ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(71):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.lpm_hint.
#    Time: 0 ps  Iteration: 0  Instance:  /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0 File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v
#  ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(72):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.lpm_numwords.
#    Time: 0 ps  Iteration: 0  Instance: /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0  File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v
#  ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(73):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.lpm_showahead.
#    Time: 0 ps  Iteration: 0  Instance: /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0  File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v
#  ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(74):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.lpm_type.
#    Time: 0 ps  Iteration: 0  Instance:  /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0 File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v
#  ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(75):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.lpm_width.
#    Time: 0 ps  Iteration: 0  Instance:  /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0 File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v
#  ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(76):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.lpm_widthu.
#    Time: 0 ps  Iteration: 0  Instance:  /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0 File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v
#  ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(77):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.overflow_checking.
#    Time: 0 ps  Iteration: 0  Instance: /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0  File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v
#  ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(78):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.rdsync_delaypipe.
#    Time: 0 ps  Iteration: 0  Instance: /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0  File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v
#  ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(79):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.read_aclr_synch.
#    Time: 0 ps  Iteration: 0  Instance: /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0  File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v
#  ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(80):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.underflow_checking.
#    Time: 0 ps  Iteration: 0  Instance: /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0  File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v
#  ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(81):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.use_eab.
#    Time: 0 ps  Iteration: 0  Instance:  /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0 File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v
#  ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(82):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.write_aclr_synch.
#    Time: 0 ps  Iteration: 0  Instance: /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0  File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v
#  ** Error (suppressible): (vsim-10000)  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v(83):  Unresolved defparam reference to 'dcfifo_component' in  dcfifo_component.wrsync_delaypipe.
#    Time: 0 ps  Iteration: 0  Instance: /compactor_tb/CompactorDUT/CompBasic/inBuffClkDomain/fifo_0  File:  /home/guille/LHCb/UT/Tell40Dev/compactor_v1/HwSrc/inputBuff2Clks/fifo_180/sim/inputBuff2Clks_fifo_180_czaw2fq.v
# Loading work.elinkfromfile(beha)
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./compactorV01_run_msim_rtl_vhdl.do PAUSED at line 27
↧

Can't generate gmon.out with gprof

June 28, 2018, 10:35 am
$
0
0
Hi all,

I'm trying to run GPROF on my project (Quartus Prime 18.0).
I have added the "enable_gprof" and "enable_exit" flags in the BSP, and I can see it does pass the -pg option when building.
I have -g and -O0 as well.
The application runs but I cannot get any gmon.out file output.

What am I missing? I have been stuck with this for hours and can't seem to figure it out...
↧

MAX 10 Internal Oscillator

June 28, 2018, 10:38 am
$
0
0
I am using a 10M2SCU169C8G demo board from QM Tech. Created an IP variation of the Internal oscillator which is supposed to output 116 Mhz. When I check the frequency, it is generating a frequency 74 Mhz
instead. Can anyone tell me why this could be happening? There are only two outputs variation of the clock available. One is 55 Mhz and the other is 116 Mhz but, that is not what it's beinggenerated.
↧
Viewing all 19390 articles
Browse latest View live
Search
<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>