Quantcast
Channel: Altera Forums
Viewing all 19390 articles
Browse latest View live
↧

Cyclone 10 GX transceiver tutorial

July 12, 2018, 5:53 pm
$
0
0
Hi,

I have cyclone 10 GX development kit. I am looking for a step by step tutorial to make a loopback design with tranceivers. I am looking for a tutorial.
↧
Search

FFT output spectrum generation

July 12, 2018, 11:36 pm
$
0
0
Hi all,

I just have a simple question regarding to FFT output. I understand that the output of the real and imag signal have signed value, and these has to be divided by exponent value in order to get the real value. The question I have is how should I get the spectrum more specifically range and the magnitude of the specific frequency! I am new to FFT core. I am looking forward to your reply! Thank you very much!

Best,
↧
↧

Extraordinary long compilation time

July 13, 2018, 7:17 am
$
0
0
Hello all.

I am compiling a relatively simple OpenCL kernel for computing SHA-1 hashes. I've optimized and got everything working under the emulator and began building an AOCX file. That was over 12 days ago. It appears to be making forward progress as 'quartus_fit' is still running 400% CPU usage and virtual memory usage is changing.

My question is, how can I tell if it will ever finish? Is there some sort of quartus_fit progress log that I can look at? Does this seem like a normal amount of time to be compiling an OpenCL kernel?

Thanks much.
↧

Quartus ip-generate command: List of available components

July 13, 2018, 9:09 am
$
0
0
Dear all,

At the moment I am trying to port a project from the Arria X to the Arria V GZ. This project contains an PCIe interface and for performing simulations, a virtual root complex is necessary. Within the project, the root complex is generated for the Arria X device via the "ip-generate" command (see below). I tried to convert the command to that of the Arria V GZ in a straight forward manner (see below), but this seems not to be working because the component "altera_pcie_a5_tbed" does not exist. I have been looking for a list of available components of the ip-generate command to see if there is a similar component available for the Arria V GZ, but I cannot find them anywhere. Do you know where I could find such a list?

Cheers,
Wendo
---
Original Arria X command (in which ip_generate is a reference to $QUARTUS_ROOTDIR/sopc_builder/bin/ip-generate)
Code:
ip_generate \
      --component_name=altera_pcie_a10_tbed \
      --output-directory=./rootport_hwtcl/ \
      --system-info=DEVICE_FAMILY=Arria\ 10 \
      --component-parameter=apps_type_hwtcl=7 \
      --component-parameter=gen123_lane_rate_mode_hwtcl=Gen3\ (8.0\ Gbps) \
      --component-parameter=lane_mask_hwtcl=x8 \
      --component-parameter=pld_clk_MHz=250 \
      --component-parameter=port_type_hwtcl=Native\ endpoint \
      --component-parameter=serial_sim_hwtcl=1 \
      --component-parameter=millisecond_cycle_count_hwtcl=124250 \
      --component-parameter=pll_refclk_freq_hwtcl=100\ MHz \
      --component-parameter=deemphasis_enable_hwtcl=false \
      --component-parameter=ecrc_check_capable_hwtcl=0 \
      --component-parameter=ecrc_gen_capable_hwtcl=0 \
      --component-parameter=enable_pipe32_phyip_ser_driver_hwtcl=0 \
      --component-parameter=use_crc_forwarding_hwtcl=1 \
      --report_file=spd:./rootport_hwtcl.spd \
      --file-set=SIM_VERILOG \
      --verbose
  #  "${SIM_ROOT}/altera_pcie_a10_tbed/altera_pcie_a10_tbed_hw.tcl" \
      --search-path=${SIM_ROOT}/altera_pcie_a10_tbed/,\$ \
      --component-parameter=millisecond_cycle_count_hwtcl=248500
Altered command for Arria V GZ:

Code:
ip_generate \
      --component_name=altera_pcie_a5_tbed \
      --output-directory=./rootport_hwtcl/ \
      --system-info=DEVICE_FAMILY=Arria\ 5\ GZ \
      --component-parameter=apps_type_hwtcl=7 \
      --component-parameter=gen123_lane_rate_mode_hwtcl=Gen3\ (8.0\ Gbps) \
      --component-parameter=lane_mask_hwtcl=x8 \
      --component-parameter=pld_clk_MHz=250 \
      --component-parameter=port_type_hwtcl=Native\ endpoint \
      --component-parameter=serial_sim_hwtcl=1 \
      --component-parameter=millisecond_cycle_count_hwtcl=124250 \
      --component-parameter=pll_refclk_freq_hwtcl=100\ MHz \
      --component-parameter=deemphasis_enable_hwtcl=false \
      --component-parameter=ecrc_check_capable_hwtcl=0 \
      --component-parameter=ecrc_gen_capable_hwtcl=0 \
      --component-parameter=enable_pipe32_phyip_ser_driver_hwtcl=0 \
      --component-parameter=use_crc_forwarding_hwtcl=1 \
      --report_file=spd:./rootport_hwtcl.spd \
      --file-set=SIM_VERILOG \
      --verbose \
      --search-path=${SIM_ROOT}/altera_pcie_a5_tbed/,\$ \
      --component-parameter=millisecond_cycle_count_hwtcl=248500
↧

Problem With Basically Everything

July 13, 2018, 11:16 am
$
0
0
Greetings,

The following forms a basis for my lack of understanding how Atlera has any market share whatsoever. I present the following points of fact regarding tool usability:


  • Graphical Incompetency
    • ​Launching a program will often spawn its respective window on the "average" of all displays, often in no-man's-land
    • Goes without saying, but: does not play nicely (at all) with multiple displays

  • CLI versions of programs function differently from their GUI "counterparts" (logically, the GUI should just be a front-end to the CLI but experimentally this does not seem to be the case)
  • System Console looks, acts like a piece of software from the early 90s
    • Obviously has a linked-list or realloc based text buffer so the longer you type/more you echo to the console, the slower it gets
    • Extremely sluggish
    • Misses keypresses frequently
    • Copy/Paste functionality is hit-or-miss

  • TCL proliferation is incomplete, shoddy at best
    • Still using TCL from 1999
    • NO DICT DATATYPE. Seriously.
    • Some tools (Qsys) interface with it, some don't

  • Newer renditions of tools essentially graphical updates to the same buggy core from decades ago
    • sopc builder -> qsys -> platform designer

  • Cryptic, unhelpful compilation messages
    • Inability to log useful information
    • No reproducibility

  • No standardization of interfaces across versions or families when it comes to IP
    • The memory interface generator. Need I say more? I could write a book on the unreliability of this IP (and to be fair Xilinx's isn't perfect either)
      • Classic: Spawning your own Xvfb (X Virtual Frame Buffer) instance to cater to the CLI generating the memory interface
        • That is right, spawning a fake display for a "CLI" program to function

    • PLLs.
    • Naming conventions all over the map - capitalization (locked, Locked, LOCKED), alphanumeric ordering, naming (clk, clock, CLK_, ck)
    • Different families seem to reinvent the wheel with no added value (altpll, the other pll, etc. etc.)

  • PLL Dynamic Reconfiguration requires a ton of extra "IP" when it could simply be memory mapped
  • Useless "devkit" resources
    • An executable file (!!) that "installs the devkit resources" (??)
    • Bloated with a ton of useless files including ones with syntax errors
    • Obviously no concern about jettisoning an "archive" of zero-value files out into the void

  • ​(The Excuse) "Factory"
    • ​All issues get routed to the, nebulous, probably non-existant, "factory"
↧
↧

Parallel Flash Loader For MAX II .

July 13, 2018, 11:58 am
$
0
0
Hi Everyone,

I am using the Parallel flash loader for CPLD to configure an FPGA using an on board NOR flash.
I have been able to generate the IP by following AN478 and AN386.

I have instantiated a flash_inst from my CPLD top file. The Flash QIP is called from the flash_inst.
My question is , do I have to generate the test bench for the flash_inst, which is calling the Flash IP?

Thank you in advance.
↧

Download Link Missing: Gzip Compression OpenCL Design Example

July 13, 2018, 12:16 pm
$
0
0
Hey Community,

Has anyone seen the download link for the Gzip Compression OpenCL Design Example? The landing page for this design alludes to having a download for Linux and Windows, but I don't see a link for either one. I tried using a browser in windows and linux and nothing shows up. I read through the reference paper and all it says is "We aim to release our implementation as a reference design which can be improved even more than the reported results." Has anyone seen the design files around?
↧

Modelsim simulation error from HLS component.

July 13, 2018, 3:53 pm
$
0
0
Hi,

I have abandoned the HLS component top module design in relation to the post I wrote below.
Therefore, I decided to design top module with Verilog and manually instantiate the generated HLS IP.
I created new empty project in Quartus Prime 17.1 standard software and added HLS IP.
Synthesis was run without error. However, a syntax error occurs in the system Verilog sub module
of HLS IP in Modelsim-Intel simulator. I know this simulator version doesn't support mixed language simulation.
Until now, I added -ghdl option to build.bat and could just check with wlf.
Is there any method to simulate in case of me?
↧
Search

Encoder for dsd audio stream in SDIF-3 format, VHDL - help a newbie

July 14, 2018, 8:59 am
$
0
0
Hello folks,

I'm a newbie in VHDL programming.
I'm trying to achieve SDIF-3 encoding from a dsd datastream coming off from an A-D conversion chip.
The dsd stream from the chip features two independent channels (L&R) data flow, plus a bitclock line.


The SDIF-3 coding scheme (see pic below), states that the channel coding splits each original bit in a 2 'semi-bit' pattern, by double the original bitclock rate.
IE: if the original bit on the source is '0', the pattern must include the original value+it's inverted, so '0-1',
if the bit value of the source stream is '1', the pattern is '10', and so on...


I was thinking of using a double-edge triggering to do the frequency doubling of the output stream, so that at the rising edge, the encoder outputs the first semi-bit value, then on the falling edge, the encoder outputs the inverted semi-bit to complete the pattern.


Please see the image attached below about the official coding scheme for this format.


I'm not sure if the code is correct, even if it is possible to do it that way.


Unfortunately I have lack of knowledge on how to simulate this.
Any help, suggestion, greatly appreciated. My code attached...

Thank you in advance! :)
Attached Images
Attached Files
↧
↧

Memory Bandwidth using HMC and HBM technologies

July 15, 2018, 12:59 am
$
0
0
I have read that HMC (Hybrid Memory cube) based memory technologies could produce memory bandwidths upto 75GB/s on Arria 10 devices. Which Arria 10 dev kit supports HMC based memory technology? I dont think Arria 10 GX dev kit supports HMC because I could only observe peak Memory bandwidth of 10GB/s.
↧

Triple Speed Ethernet (1000-Mbps) : transmit Jumbo frames?

July 15, 2018, 5:21 am
$
0
0
Hello all.

I was working on a project with Triple-Speed Ethernet IP Core, and I'm having a bit of trouble understanding how to send jumbo frames. I built the system on Qsys with Triple Speed Ethernet (10/100/1000-Mbps) with two SGDMA modules for packet generation/extraction.

The Triple-Speed Ethernet IP Core User Guide shows that, on 10.5 Using Jumbo Frames, frm_length[15:0] (Dword offset 0x05) register should be set to 9600 (which would be 0x2580).

So I software-initialized with *(tse_base+0x05) = *(tse_base+0x05) | 0x2580;
Then used API Function alt_avalon_sgdma_construct_mem_to_stream_desc() with byte length 16+9600.

I can see that the packet is being sent (looking at the LED on my FPGA board), but nothing being received on Host PC.
Tried loopback receive too but nothing showing up.

Is this the right way to send Jumbo Packets with Triple-Speed Ethernet? I will need to check problems with receive, but I wanted to make sure there isn't a problem with transmit.

Thank you.
↧

Compiling OpenCL kernel in Fedora 28

July 15, 2018, 6:23 am
$
0
0
Hi,

I have installed OpenCL SDK in my Fedora 28. But while trying to compile the kernel I am getting the following linking error,

Quote:
[sumanish@black vector_add]$ aoc -march=emulator -v -board=a10gx device/vector_add.cl -o bin/vector_add.aocx
aoc: Environment checks are completed successfully.
aoc: Cached files in /var/tmp/aocl/sumanish may be used to reduce compilation time
You are now compiling the full flow!!
aoc: Selected target board a10gx
aoc: Running OpenCL parser....
/home/sumanish/Intel_FPGA_OpenCL_SDK/Examples/exm_opencl_vector_add_x64_linux/vector_add/device/vector_add.cl:23:48: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance
__kernel void vector_add(__global const float *x,
^
/home/sumanish/Intel_FPGA_OpenCL_SDK/Examples/exm_opencl_vector_add_x64_linux/vector_add/device/vector_add.cl:24:48: warning: declaring kernel argument with no 'restrict' may lead to low kernel performance
__global const float *y,
^
2 warnings generated.
aoc: OpenCL parser completed successfully.
aoc: Linking Object files....
aoc: Compiling for Emulation ....
/usr/bin/ld: cannot find crtbeginS.o: No such file or directory
/usr/bin/ld: cannot find -lgcc
/usr/bin/ld: cannot find -lgcc_s
aocl-clang: error: linker command failed with exit code 1 (use -v to see invocation)
Error: Optimizer FAILED.
Refer to vector_add/vector_add.log for details.


[sumanish@black vector_add]$
Which thing I am missing ? Please help.

Regards,
Sumanish
↧

DE5aNet-DDR4 opencl17.1 setup question

July 15, 2018, 7:20 am
$
0
0
I"m trying to set up my DR5aNet DDR4 FPGA board. I installed OpenCL and Quartus Prime properly, following the manual. But the problem is I cannot compile a test project of fft1d.cl into fft1d.aocx.

My setup specification is here.
Code:
CentOS 7.0.1406
linux kernel 3.10.0-123.20.1.el7.x86_64

aoc -version: Version 17.1.0 Build 240
aocl version: aocl 17.1.0.240
Licensed Quartus prime 17.1.0 Build 240
And I got following errors after executing this command `aoc device/fft1d.cl -o bin/fft1d.aocx -fpc -no-interleaving=default -board=de5a_net_ddr4 -v`.
Code:
aoc: Environment checks are completed successfully.
aoc: If necessary for the compile, your BAK files will be cached here: /var/tmp/aocl/
You are now compiling the full flow!!
aoc: Selected target board de5a_net_ddr4
aoc: Running OpenCL parser....
aoc: OpenCL parser completed successfully.
aoc: Optimizing and doing static analysis of code...
aoc: Linking with IP library ...
Checking if memory usage is larger than 100%
aoc: First stage compilation completed successfully.
Compiling for FPGA. This process may take a long time, please be patient.
Error (17941): The design could not be loaded due to errors.
Error: design::import_design -file base.qdb -overwrite  failed!
Error (23031): Evaluation of Tcl script /opt/intelFPGA_pro/17.1/quartus/common/tcl/internal/qatm_import_design.tcl unsuccessful
Error: Quartus Prime Compiler Database Interface was unsuccessful. 3 errors, 4 warnings
Error (23031): Evaluation of Tcl script import_compile.tcl unsuccessful
Error: Quartus Prime Compiler Database Interface was unsuccessful. 1 error, 0 warnings
Error: Compiler Error, not able to generate hardware
In addition, this is `bin/fft1d/quartus_sh_compile.log`
Code:
Info: *******************************************************************
Info: Running Quartus Prime Compiler Database Interface
    Info: Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition
    Info: Copyright (C) 2017  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions
    Info: and other software and tools, and its AMPP partner logic
    Info: functions, and any output files from any of the foregoing
    Info: (including device programming or simulation files), and any
    Info: associated documentation or information are expressly subject
    Info: to the terms and conditions of the Intel Program License
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Sun Jul 15 20:54:30 2018
Info: Command: quartus_cdb top -c base --import_design --file base.qdb --overwrite
Info: Quartus(args): --project top -c base --file base.qdb --overwrite
Info: Using INI file /root/intelFPGA_pro/17.1/hld/board/de5a_net_ddr4/tests/fft1d/bin/fft1d/quartus.ini
Info: Running design::import_design -file base.qdb -overwrite
Critical Warning (18639): Skipping database version check for import of database files from  'Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition'. The imported database might be incompatible with current version of the software.
Critical Warning (18639): Skipping database version check for import of database files from  'Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition'. The imported database might be incompatible with current version of the software.
Critical Warning (18639): Skipping database version check for import of database files from  'Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition'. The imported database might be incompatible with current version of the software.
Critical Warning (18639): Skipping database version check for import of database files from  'Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition'. The imported database might be incompatible with current version of the software.
Info (16677): Loading final database
Info (16734): Loading "final" snapshot for partition "root_partition".
Error (17941): The design could not be loaded due to errors.
Error: design::import_design -file base.qdb -overwrite  failed!


Error (23031): Evaluation of Tcl script /root/intelFPGA_pro/17.1/quartus/common/tcl/internal/qatm_import_design.tcl unsuccessful
Error: Quartus Prime Compiler Database Interface was unsuccessful. 3 errors, 4 warnings
    Error: Peak virtual memory: 2525 megabytes
    Error: Processing ended: Sun Jul 15 21:13:13 2018
    Error: Elapsed time: 00:18:43
    Error: Total CPU time (on all processors): 00:18:46
Info: *******************************************************************
Info: Running Quartus Prime Compiler Database Interface
    Info: Version 17.1.0 Build 240 10/25/2017 SJ Pro Edition
    Info: Copyright (C) 2017  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions
    Info: and other software and tools, and its AMPP partner logic
    Info: functions, and any output files from any of the foregoing
    Info: (including device programming or simulation files), and any
    Info: associated documentation or information are expressly subject
    Info: to the terms and conditions of the Intel Program License
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Sun Jul 15 20:54:29 2018
Info: Command: quartus_cdb -t import_compile.tcl
Info: Using INI file /root/intelFPGA_pro/17.1/hld/board/de5a_net_ddr4/tests/fft1d/bin/fft1d/quartus.ini
Info: Checking for OpenCL SDK installation, environment should have INTELFPGAOCLSDKROOT defined
Info: INTELFPGAOCLSDKROOT=/root/intelFPGA_pro/17.1/hld
Error (23031): Evaluation of Tcl script import_compile.tcl unsuccessful
Error: Quartus Prime Compiler Database Interface was unsuccessful. 1 error, 0 warnings
    Error: Peak virtual memory: 777 megabytes
    Error: Processing ended: Sun Jul 15 21:13:13 2018
    Error: Elapsed time: 00:18:44
    Error: Total CPU time (on all processors): 00:18:46
Thanks in advance for your help!
↧
↧

Can i just power the fpga part of the soc chip？

July 15, 2018, 5:47 pm
$
0
0
Hi，I plan to design a system with Arria10 SoC，Can I just power the FPGA part and leaving the HPS Part shut down?
Thanks.
↧

The L4 Watchdog Module Address Map is not exact in the hps.h

July 16, 2018, 2:31 am
$
0
0
Hello,
I would like to use header in my application using Altera Cyclone V.
In the Cyclone V Hard Processor System Technical Reference Manual I can find this information about the Watchdog:
L4 Watchdog Module Address Map
Registers in the L4 Watchdog module
Module Instance Base Address
l4wd0 0xFFD02000
l4wd1 0xFFD03000
But in the following header file the address does not correspond:
7 816: #define ALT_L4WD0_OFST 0xffd00200
7 859: #define ALT_L4WD1_OFST 0xffd00300
Is that the good header file?
What can I do?
Thanks for your help
Jerome
↧
Search

Cache invalidation APIs and its usage in Altera Cyclone V SOC Linux

July 16, 2018, 4:59 am
$
0
0
Hi all,

We are conducting a feasibility study on our Altera Cyclone V SOC.
We are having some streaming data receiving at FPGA at 300 Megabits per second.
We have to transfer this data without any packet loss to a server machine over WiFi connection.
UDP client application works on Altera SOC and server application works on an Ubuntu desktop machine.

Initially we tried out a sample UDP_client and UDP_Server application which sends hardcoded buffer of data [from user space only. Not data read from FPGA via kernel space] to measure the maximum data rate over WiFi.
We got the range of 250Mbps to 500Mbps. [Without tuning and tuning some network parameters as suggested in the link [https://opensourceforu.com/2016/10/n...e-monitoring/]

We are running Angstrom Linux supplied by Altera (Linux kernel version 4.9).

We are using interrupt driven design with FPGA writing data to a ring buffer implemented in DDR.
This ring buffer is mmapped to user space during application start.

We are experiencing data miss which we later found that data is actually missed even between kernel space and user space.
Hence we limited our analysis to client side by commenting out the send() function to server.

On analysing the sequence numbers, we understood that some of the sequence numbers are stale data residing in the memory.
This we have confirmed by doing a simple exercise.

After reading each data packet including sequence number, we write the sequence number back to memory as zero.
When we run this code, sequence number mismatch is not seen.

We would like to know how can implement this in software by including any cache invalidation routines.
We have tried out APIs like __cpuc_flush_kern_all(); and flush_cache_all(); before every time informing FPGA to write data to DDR.
But these APIs do not work.

Could you please help us with the cache invalidation APIs and the exact workflow in which cache invalidation APIs are to be used in Altera Linux SOC?

Thank you,
Lullaby
↧

"Can't elaborate user hierarchy auto_fab_0" on adding signal_tap

July 16, 2018, 6:41 am
$
0
0
Hi,

I have a design that uses some Altera RTL and some of my own RTL.

I am trying to add a few signals to Signal Tap, but on Analysis and Elaboration, I get this error:

"Error(13869): VHDL Binding Indication error at altera_mf_components.vhd(4895): design entity "altsyncram" does not contain generic "stratixiv_m144k_allow_dual_clocks" specified in associated component "
"Can't elaborate user hierarchy auto_fab_0"
"Error(19882): Automatic debug logic insertion has failed. "

If I remove all the signals from Signal Tap this error goes away.

I need to get around this error to debug on Signal Tap. Help?
↧
↧

ddr3 RTL example of DE10 nano board

July 16, 2018, 8:12 am
$
0
0
Hiii every one ,



I try to compile the example DDR3 RTL of DE10 nano board using quartus V16.0 but I get this warning :
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.


and the .sof file was not generated

so why the file was not generated and what does mean this warning
↧

Stratix II NIOS II devkit reference manual

July 16, 2018, 11:28 am
$
0
0
Hello,
I have old Nios Development Board Stratix II Edition (version 6XX-09900-0D), but I can't find reference manual for this version of the board. I found only this: https://www.altera.com/content/dam/a..._2s60_rohs.pdf, but this documentation is not suitable for my board (I need FPGA pinout).
Where can I get a manual for my version of the board?
Thanks
↧

Getting Quartus to recognize a Recirculation Mux Synchronizer

July 16, 2018, 12:58 pm
$
0
0
Hi all,

I'm attempting to perform a CDC of a Data bus that switches values with a Write Strobe using a "Recirculation Mux Synchronizer". In essence the Write Strobe is synchronized across the Async clocks and the synchronized pulse is then used as an enable on the Data bus latching clock (similar to what is shown in the attached image).

The "Managing Metastability with the Intel Quartus Prime Software" section of the Quartus Handbook, the tool has the capability to recognize a Synchronization Register Chain. As such, I would expect the tool to ignore timing this path, but that's not whats happening. Since the Data latching flop uses an enable that is synchronized to the latch clock, shouldn't the entire path be ignored if the tool recognizes the synchronization register chain? Am I misunderstanding this?

If not, then is there a way to make Quartus recognize this as an Async path without setting Async clock groups, false paths or multicycle paths? This is for IP that will be instantiated inside a top level design and I was hoping to set individual exceptions across nodes.

Thanks for your help!
Attached Images
↧
Viewing all 19390 articles
Browse latest View live
Search
<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>