Hello,
I am a functional verification engineer who is trying to verify as much as possible using Questa simulators prior going to the LAB. I am using UVM for custom logic verification. When integrated in the Altera SoC, the main verification will be done in the LAB. I am trying to shift some of my integration and bring up efforts to the simulation world rather than the LAB.
Does Altera provide any digital simulation model for its SoC? I would like to simulate some code that I have written for ARM core in C, prior going to the lab. Is there a way to load the program into the memory and reset the ARM core to execute my code in simulation so I can clean up basic bugs prior to the lab?
Any suggestion is highly appreciated.
Regards,
AA
I am a functional verification engineer who is trying to verify as much as possible using Questa simulators prior going to the LAB. I am using UVM for custom logic verification. When integrated in the Altera SoC, the main verification will be done in the LAB. I am trying to shift some of my integration and bring up efforts to the simulation world rather than the LAB.
Does Altera provide any digital simulation model for its SoC? I would like to simulate some code that I have written for ARM core in C, prior going to the lab. Is there a way to load the program into the memory and reset the ARM core to execute my code in simulation so I can clean up basic bugs prior to the lab?
Any suggestion is highly appreciated.
Regards,
AA