Image processing on nios 2
Hello everyone I want to implement edge detection algorithms in c language in nios 2. Can you guide me some reference so that I can learn image processing on nios 2 . Thanks
View ArticleQuartus did not work on 64-bit redhat enterprise linux 7.2
Downloaded and installed bittware software for opencl FPGA board. 1. installed bw2tk-1.9-20849.el7.x86_64.rpm 2. using bwconfig-gui, loaded top.rbf from hello_world_d5 to flash0 memory of device. 3....
View ArticleAny explanation of APPLYCFG bit of SDRAM control register in Cylcone V
I have been working on transferring data from HPS SDRAM to FPGA on DE1-SoC board. I followed the steps here https://www.google.co.kr/url?sa=t&rc...17218890,d.dGY well the transferring works fine,...
View ArticleOnly one core in Linux in web-edition?
I've noticed while going back and forth from Windows to Linux on a development machine, that Quartus on Linux complains that "parallel compilation is not licensed and has been disabled", while on...
View ArticleProblems running sdram pin assignment tcl script on Linux
I'm generating a HPS setup for a Cyclone V device. When I run the auto generated script soc_system/synthesis/submodules/hps_sdram_p0_pin_assignments.tcl it fails. In Quartus command-line the failure is...
View ArticleQuartus II Source control/ version control
Hi, I am primarily a software engineer beginning to work on Quartus II for Cyclone II. What kind of version control tools are available for design files? I am familiar with Tortoise SVN. Is there a...
View ArticleCan't access altera training
So I went to access the altera training site today and I cannot access any of the courses. Is this something that is expected to be resolved any time soon or is it a problem on my end? Using Firefox on...
View ArticleSPI in full-duplex mode with alt_avalon_spi_command()
Dear all, I have a problem using the alt_avalon_spi_command() in full-duplex mode. Is it possible at all ? If so, how to do it ? If no, what other possibilities do I have ? Implementation in VHDL ?...
View ArticleTrouble running OpenCL HelloWorld example on emulated s5_ref
I'm struggling to get the Hello World example running on emulated s5_ref. I have successfully compiled the kernel with no errors, and have also compiled the host applications (using Visual Studio 2013...
View Articlequartus prime fixed license expiration
Hi, It is not clear to me what is the fixed license expiration date of Quartus Prime Standard edition. After the 1 year timeframe, is the software usable but without updates, or it stops working and...
View Articlefitting error
Hellow every body During compilation of my design, I find an errore of "Error (170143): Final fitting attempt was unsuccessful" that the dveice canot rout some signals. Although the resources is small...
View ArticleMAX 10 Jtag Problem
Dear Good people My MAX 10 JTAG was working well but suddenly from yesterday it is showing some problem. When i push the button auto scan it is showing "Unable to scan device, Cant scan JTAG chain"....
View ArticleColumn Scanning Matrix in VHDL
Hi, I am new to VHDL. If I had 3x3 matrix say: 110 010 001 How would I check the row numbers which contain their first one starting from scanning the bottom left element in the matrix and moving up...
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Test Pattern Generator -> Clocked Video Output with Altera NEEK
I have an Altera FPGA NEEK and I want to use the following VIP cores setup: CVI(Clocked Video Input) -> SCL(Scaler) -> FB(Frame Buffer) -> CVO(Clocked Video Output). This gives me a screen...
View Articledigital simulation model for Altera SoC (Arria 10)
Hello, I am a functional verification engineer who is trying to verify as much as possible using Questa simulators prior going to the LAB. I am using UVM for custom logic verification. When integrated...
View Articlejtag user0/user1 registers in VHDL logic
How do I define the jtag user0/user1 registers in my vhdl code on CycloneIV? What are the signal names are for at least tdi/tdo and the 'shiftdr' state, for use from VHDL? In other words, what is...
View ArticleTimeQuest Tutorial Design Idea
Personally I find TimeQuest to be the cruelest imposition foisted on Mankind since the advent of time itself. What would be nice is a tutorial project starting with a pair of D FlipFlops...
View Articlebpsk demodulator with phase lock
Hi, i want to realize a bpsk demodulator for a receiver tha is not coherent with the transmitter, so the phase of the receiver's local oscillator could be unknown. I read about costas loop but i don't...
View ArticleAvalon MM Interface readdata signal [511:0]
Hello, I am trying to read data from the global memory using a pointer. This memory address pointer (64 bits) is an output from my master module and tries to read data from the slave. The values stores...
View ArticleHow to program a EPM7128ATC100-6 Cpld (Max 7000 series)? I can't find it in...
Hi, I have some EPM7128ATC100-6 and I want to use them in a little project. I'm using Quartus 13.0sp1 because seems this is the last version that supports the Max 7000 series. But I can't find this...
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