Profiler error: Incompatible AOCX
I am trying to run the profiler on a kernel but I get the error: Incompatible AOCX file, quartus report information not available Please regenerate your AOCX file with the latest version of the aoc...
View ArticleOpenCL Licence
Hi, How can I verify that I have valid licence for OpenCL SDK? Is there any command or setting? I am using windows 7.
View ArticleHelp to understand PCIe Host PC frequency
Hi people, I need some help to understand the PCIe clock frequency on host PC's. According to PCIe Sig, the PCIe clock frequency should be 100 MHz +- 300 ppm. Then, to follow this recommendation, i...
View ArticleArria 10 GSRD board - unable to write reg or mem via Linux
I've got the Arria 10 GSRD board. I'm running from a pre-built SD card image created by following instructions on the rocketboards site for the A10 GSRD, which I can't link here. The page here shows...
View ArticleFitter Report - Caret character - what does it mean?
Compiling for a C 5 SOC chip and in the fitter reports, "All package Pins" section, there is a '^' (caret) character that precedes signals. What does it mean? See below example: V4 36 3A ^DCLK Weak...
View ArticleMAX 10 - ADC pins as GPIO
Hi. I've a doubt about MAX 10 dual supply. To use the both AD converters, it's necessary to put 2.5V on bank 1A and on bank 1B. But, if only the ADC1 is necessary, the bank 1B can be GPIO in 3.3V? I...
View ArticleWhy do the number of VCCIO and GNDIO pairs more than number of banks in a...
I assumed that there is a VCCIO for each bank. However, it seems that a single bank can have multiple VCCIO and GNDIO connections. As far I understand a single bank shall have a single IO voltage which...
View ArticleCreating Video Output
Hello guys! I know, there is a bunch of threads around, speaking of how to create a basic video output, but none of the templates/instructions worked for me. Also I'm quite new to FPGA, Verilog and the...
View ArticleQSYS Comments?
Hello, I am a beginner Quartus user, and I've been playing around with some example projects for the MAX 10 Deca Kit. One thing about QSYS I've found so far, is that aside from the names, there is not...
View ArticleProgram FPGA from EPCS, and boot Linux from SDCard?
Given a Cyclone V SoC (HPS) with a EPCS and SD-Card. Is it possible to setup FPGA to load config from EPCS, while booting Linux from the SD Card without reprogramming the FPGA?
View ArticleIOPLL rst input
I instantiated an IOPLL in an Arria 10 SoC design and tried to tie the rst input to logic 0. Quartus Prime won't let me do that. I don't want to reset the PLL and the user guide does not say that a...
View ArticleWhere is the PWM core/ip?
Hi all, I thought there will be a PWM core/ip in Quartus Lite 15.1 (Qsys) but I think I'm wrong. Unless it has a weird name that I can't figure out. Is there one? Thanks
View ArticleAccessing individual nodes in a bus
Hi How can the individual nodes on a bus be accessed? Is using LPM_DECODE the only way? Thanks
View ArticleDE1 - checking SRAM?
Hello, I own a DE1 board and would like to test the onboard SRAM. I'm using the board for learning/hobby, and having issues with the SRAM use I'm currently split between bad design or faulty chip. (I'm...
View ArticleA synchronous clear enable conter RTL
I have issues with RTL of simple counter: a synchronous clear enable counter. I use Altera template to be confident as much as possible. http://quartushelp.altera.com/14.1/m...o_counters.htm...
View ArticleLPDDR2 Interfacing to CycloneV
Hi, In general, from Board design perspective, What is the process (with quartus SW) for planing LPDDR2 interface on CycloneV? For example how to determine which BANK/IO to use Thanks
View ArticleMax 10 Development Kit DAC
Hey all, first of all, I'm new to programming with Quartus. I want to sample a signal with one of the ADCs on the Max 10 Development kit. After that, I want to convert the descrete signal again to an...
View ArticleUART Examples for MAX10M 50 DA F 484 C 6 GES
Hi All, Am learning FPGA. So far, I have done blinking LED with uC OS tasks switching. [ from Qsys->Quartus->Nios II]. It is working fine. I took help from materials from altera site. Now, am...
View ArticlePossible virus BoardTestSystem32.exe
Hello, We have stopped an application from running called BoardTestSystem32.exe. The binary was located in the directory: C:\altera\14.1\kits\arriaVST_5astfd5kf40_soc_orig\...
View ArticleFitter error: can't place fractional PLL in Cyclone V ST.
Hi, I have a design that uses the Hard Memory interface for the HPS and for the FPGA DDR memory. If I add a regular PLL to this design from an I/O pin in bank 3A (bank 3B and 4A are the DDR banks for...
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