jtag user0/user1 registers in VHDL logic

How do I define the jtag user0/user1 registers in my vhdl code on CycloneIV?
What are the signal names are for at least tdi/tdo and the 'shiftdr' state, for use from VHDL?

In other words, what is Altera's version of Xilinx's 'bscan' component?

I have searched, but only found references to 'virtual jtag megawizards', which (as far as I understand)
build a huge edifice on user0/user1, when I just want to use user0/user1 'raw'.