Setting Tco and Tsu constraints, DE0-nano

Hi All,

As part of the process of attaching University Program -> Memory -> SD Card Interface SOPC IP module to a NIOS processor I noted " it is important to set Tco and Tsu constraints for the SD card ports. Both parameters should be set to not more than 10ns" from the document "Altera University Program Secure Data Card IP Core".

The SD card interface is implemented using 4 pins, (CLK, output from NISO II), and (DAT0, DAT3 and CMD, all BIDIR to/from NIOS II).

Using the TimeQuest wizard, su/th 8ns was entered for the BIDIR pins, the resulting SDC file is shown below. Is this the correct process for entering these parameters ?

To further complicate the issue, the SOPC has a clock module "Clock Signals for DE-series Board Peripherals" which is used to shift the 50MHz input clock 3ns(?) as required by the University Program SDRAM interface. The module output is used to driver all NIOS components, as well as provide a skewed clock to the SDRAM.

Given that SD card interface is driven with this skewed clock, presumably there is a further level of complexity associated with setting Tco and Tsu ?

Thoughts and comments on these issues are most appreciated.

Thanks,

Mark

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SDC file settings:

# Clock constraints

create_clock -name "NIOS_clk" -period 20.000ns [get_ports {ext_clk_50}]


# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks

# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty

# tsu/th constraints

set_input_delay -clock "NIOS_clk" -max 12ns [get_ports {SD_EXT_DAT3}]
set_input_delay -clock "NIOS_clk" -min 8.000ns [get_ports {SD_EXT_DAT3}]
set_input_delay -clock "NIOS_clk" -max 12ns [get_ports {SD_EXT_CMD}]
set_input_delay -clock "NIOS_clk" -min 8.000ns [get_ports {SD_EXT_CMD}]
set_input_delay -clock "NIOS_clk" -max 12ns [get_ports {SD_EXT_DAT0}]
set_input_delay -clock "NIOS_clk" -min 8.000ns [get_ports {SD_EXT_DAT0}]