Hi all,
While running a design verification generated via qsys testbench, I'm continuously monitoring sink bfm for any new data/packet. During this, i get this warning.
*** WARNING: vl_init_value, unknown TD kind:0
I get it frequently, but not always. I'm not getting whether it is warning related to design(Quartus Design Files) or Modelsim.
It doesn't affect the verification but gets replicated in transcript multiple times that it gets difficult to analyze the printed output data.
Any leads will be helpful. Thanks in advance!
While running a design verification generated via qsys testbench, I'm continuously monitoring sink bfm for any new data/packet. During this, i get this warning.
*** WARNING: vl_init_value, unknown TD kind:0
I get it frequently, but not always. I'm not getting whether it is warning related to design(Quartus Design Files) or Modelsim.
It doesn't affect the verification but gets replicated in transcript multiple times that it gets difficult to analyze the printed output data.
Any leads will be helpful. Thanks in advance!