Hi folks,
Searching for a stubborn error, I came across the following behavior:
When an avalon memory mapped master (for example NIOS) writes to an address, that is not mapped to any qsys component, the write will not get lost (as I would expect it), but any random component will get assigned!
By looking at the technology map, I can see the reason: Qsys interconnect does not perform full address correlation, but only checks on certain bits that are expected to get used.
Of course if someone writes to an unmapped memory address, there must be a problem with the code or something.
But anyway - is there a simple way to prevent random components to get accessed, when writing to an unmapped memory area?
Best Regards,
Simon
Searching for a stubborn error, I came across the following behavior:
When an avalon memory mapped master (for example NIOS) writes to an address, that is not mapped to any qsys component, the write will not get lost (as I would expect it), but any random component will get assigned!
By looking at the technology map, I can see the reason: Qsys interconnect does not perform full address correlation, but only checks on certain bits that are expected to get used.
Of course if someone writes to an unmapped memory address, there must be a problem with the code or something.
But anyway - is there a simple way to prevent random components to get accessed, when writing to an unmapped memory area?
Best Regards,
Simon
