Hello,
I have used two clocks in my design.Both clocks are generated from same PLL.Clock frequency of one clock is 50MHz and frequency of other is 55MHz.I am transferring data between 50MHz and 55MHz. I have taken care of CDC in my design.My question is
(1) Can I provide false path between two clocks? In one of the post, I read that PLL output clocks are synchronized with PLL input and synchronize with each other
as well.
(2) How 50MHz and 55MHz clocks can be synchronous? Does timequest look for the repetitive pattern and based on that it decide whether clock is synchronous or asynchronous?
(3) I have taken care for the naming convention while transferring data from one clock domain to another clock domain.So based on that I can provide false path between nodes.
Regards,
Krupesh
I have used two clocks in my design.Both clocks are generated from same PLL.Clock frequency of one clock is 50MHz and frequency of other is 55MHz.I am transferring data between 50MHz and 55MHz. I have taken care of CDC in my design.My question is
(1) Can I provide false path between two clocks? In one of the post, I read that PLL output clocks are synchronized with PLL input and synchronize with each other
as well.
(2) How 50MHz and 55MHz clocks can be synchronous? Does timequest look for the repetitive pattern and based on that it decide whether clock is synchronous or asynchronous?
(3) I have taken care for the naming convention while transferring data from one clock domain to another clock domain.So based on that I can provide false path between nodes.
Regards,
Krupesh