How does the ADC I/O on Cyclone V GX Starter Kit Work?`
I used the system builder and it generated the Verilog I/O as follows: //////////// ADC SPI ////////// output ADC_CONVST, output ADC_SCK, output ADC_SDI, input ADC_SDO, I read the LTC2308 and I am...
View ArticleSharing the ASMI interface problem
Hi, I am trying to get access to the external SPI flash (EPCQ256) from a microcontroller through the Cyclone V fpga. I have created the altera_serial_loader IP block to get access to the flash. I am...
View Articlewhy not NIOS II processor is not available in the Quartus II 14.0 and above...
why not NIOS II processor is not available in the Quartus II 14.0 and above aditions
View ArticleEclipse console clears error messages too early.
Hello, I am having some trouble downloading my software to my De0-CV. Eclipse shows errors during its download process but clears these messages immediately. Then i get the message: "Download elf...
View ArticleError: (vsim-3828) Could not link vsim_auto_compile.dll
Good Morning, I created a system by means of the Quartus Qsys composed by a SoC (hard processor system - hps) and an Avalon Slave. The Qsys generated all the files for synthesis and simulation,...
View Articlecyglone 5 gt interface for ads5263
Hello. Is there a ready block to connect the cyclone_gt to the adc ads5263? The device ads5263 have 4 channels analog input, and each channel has 2 ddr lvds outputs lanes. then i have: 1 bitclock wire...
View ArticleDE0-Nano Demo #2
Hi, there any chance to get the vhdl code of - DE0-Nano Demo #2: Analog to Digital Conversion. https://www.youtube.com/watch?v=SPXXpBRVLsE thank you David
View Articlealtera v gt board
i am using Altera's Arria V GT FPGA Development Kit , how to access SMA TX port directly from FPGA without using GUI of board.
View ArticleArria V GT FPGA
i am using Altera's Arria V GT FPGA Development Kit , how to access SMA TX port directly from FPGA without using GUI of board.
View Article88e1111 on custom board
Hi everyone, i'm facing a problem using 88e1111 on a custom board i produced. I copied most of things on de2 115 especially on 88e1111 side. I m using lwip in superloop mode and this is working fine on...
View ArticleNeed help to provide timing constraint and understood the working of Timequest
Hello, I have used two clocks in my design.Both clocks are generated from same PLL.Clock frequency of one clock is 50MHz and frequency of other is 55MHz.I am transferring data between 50MHz and 55MHz....
View ArticleChange buswidth on the hps2fpga bridge
Hi, I am trying to enable the hps2fpga bridge using 64 bits instead of 32 bits, From qsys and fpga side everything seems fine but i am not sure what i have to do on linux side in order to really enable...
View ArticleHow to interface my verilog code with FFT ip core
I'm working on an application that involves the FPGA to take in an analog signal through its onboard ADC and perform the FFT using the altera ip core. So far, my understanding is the ip core generates...
View ArticleSubscription edition of Quartus 13.1 ?
Hi all, So I have a 32 old boards, each with 8 stratix-3 '150-1 chips on them from a past project where I didn't do the design, it seems like there's still some stuff I could do with that sort of FPGA...
View ArticleVGA help!!!
hi there! during my final project i'm trying to build a sniffer (network analyzer) with the DE-2 board and niosii, i wrote a code for the sniffer and add it to the DE2_net example, now the next level...
View Articleunderstanding avalon slave master transfers
Hello, I am trying to understand how avalon slave <-> master read and writes are working, I have seen the master and slave templates and several manuals and sheets and posts about that but I am...
View Articletutor
Hello i need help about a projekt. Its at the end but i have to simulate it so that i know where i have maked a mistake.But i havent ever worked with modelsim and dont have time to learn it alone....
View ArticleNo ROM initialization (FIR, NCO coeffecients, etc.) on MAX10 SCE Compact...
Hi, The MAX 10 Configuration User Guide states on page 2-2 that MAX 10 devices with "Compact" feature options do no support memory initialization. I would like to use a 10M50SCE (I like the SCE price...
View ArticleAvailability of MAX 10 devices in 144-EQFP packages?
Currently, www.buyaltera.com lists only 19 available parts for a single MAX 10 device, 10M08SCE144C8G, that uses a 144-EQFP package. No other vendor according to www.octopart.com or www.findchips.com...
View ArticleProblems due to floating point matrix multiplication megafunction
All dear colleagues, I need to instantiate an Altera float-point matrix multiplication megafunction in my Verilog design, and plan to input control signals generated by one-hot state machine. The two...
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