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FIR II Compiler propagation delay
Hello, I am using the single channel FIR II with 50 taps coefficients. I expect to get 50 samples delay between input and output data. However with the ModelSim simulation waveforms I can see that at...
View ArticleHow to control "ready" signal of exported Av-ST using Nios II for simulation?
Hello, I'm trying to simulate the Frame Buffer II IP core with runtime control by Nios II on ModelSim. I create my system on Qsys and run the simulation through "Nios II Software Build Tools for...
View ArticleNIOS SDRAM and DE2 board boot
Hi, i have a niosii using SDRAM because the memory inside cyclone ii is not sufficient. All is fine. The hardware and the software run fine but now i would like that the board boots on this project...
View ArticleCyclone V partial reconfiguration support
We planned to use partial reconfiguration with the Cyclone V series of SoC-FPGAs. Now the Cyclone V Device Overview (CV-51001) states that Quote: The partial reconfiguration feature is available for...
View ArticleOpenCL Compiler goes out of memory, gives compiler error
Hi, I am using OpenCL SDK 15.1 When Compiling a kernel code with unrolled loops or more than 1 compute unit, the quartus-syn or quartus-fit processes go out of memory, and then get killed by kernel....
View Articlehow to access fpga fabric from linux
hello, I am using cyclone V Installed linux on cortex , but now i am confused that how to access fabric(user logic) from linux,do i need to write kernel driver for this or should i change in bootloader...
View ArticleMAX7000 GCLRn dedicated pin
Good day, I am currently developing a small application with MAX7000S CPLD. I would need to enable dedicated GCLRn pin to clear all design registers but cannot find how to do this. cheers Carlo
View Articleerror 10161 when importing vhdl packages to system verilog
Hi, My toplevel design is in system verilog, I import a VHDL package with record type, quartus errors with "Error (10161): Verilog HDL error at dummy_sysver.sv(3): object "dummy_vhd_pkg" is not...
View Article[Question] TCL script with Altera Monitor Program
Hello, I'm an electrical engineering student, and i'm currently doing a project with the DE0-Nano SoC. I was asked to do a TCL script, which will automatically execute several times an application on...
View ArticleFlash Programmer - Error 8, MAX10
Hello, I am trying to write an application into the CFM Space in my Max10 (10M50DAF484C6 on the Development Kit board) made with NIOS2 SBT with the flash programmer and get the error 8. What i read in...
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SGDMA transfer from and to Dualclock FIFOs
Hi, we are searching for a fast DMA solution that will fit into a ALTERA EP4GX15BF14Cx chip and is compatible to the PCIe design in http://www.alterawiki.com/uploads/3/...cie_gen1x1.zip to transfer ADC...
View ArticleHow to PING a computer host from NIOS
Hi, We are trying to PING a PC from the NIOS as a part of our application debug process. Is that possible, if so please suggest me how to do it or any link or pdf that I can follow. Thank you.
View ArticleDE1-SoC - HPS DMA example
Hi, I've been trying to run the HPS DMA for the Cyclone V SoC Development kit on De1-SoC, however, I've been having many issues. I've tried building the project in DS-5 as described in the readme file...
View ArticleError: Peak virtual memory: 255 megabytes (Quartus)
Hi I have a problem every time command to simulate I get this error. Al copilar not give me any error. Only when command to simulate someone who can help me? FPGA Code: Info: Running Quartus II...
View ArticleWhy can't access Self Service Licensing Center
Hi, all I just buy a new modelsim license, but when I login the altera account, I click Self Service Licensing Center, but nothing happened, I have try different computer and different network for...
View ArticleVersion Control Files for Altera IP
I am using Quartus 16.0 and would like to only store in version control the necessary files needed for Altera IP (this includes files for simulation). I tried only storing the .QSYS and .SOPCINFO...
View ArticleDDR3 simulation for ArriaVSX
hello there. I have a question. I am simulating DDR3 IP-core. I found README.txt in "*example_design/simulation" directory. I tried to simulate IP core and example design according to what it says....
View Articlesimulating crc error using ederror_inject jtag instrucrion
Hi all, I am trying to verify the crc feature for SEU mitigation in Stratix IV device . While trying to inject error using ederror_inject jtag instruction , the data being written into fault injection...
View ArticleFast data tranfer to PC
Hallo, I am trying to implement a new project where I want to use an FPGA as a kind of DAQ system. Basically the FPGA is reading about 70 sensors sending asynchronously with a maximum bit rate of...
View ArticleUpdating OpenCL fpga image
Hi, Can someone tell me is it possible to to add some small logic to an OpenCL built FPGA image after its built. Is it possible to take the openCL FPGA image and update it in any way. It would be very...
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