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Can't launch ModelSim on Ubuntu. Can't find license file
Hi all, I have recently installed Quartus II 14.1 and ModelSim Starter Edition on an Ubuntu 16.04 distro. I have tried to launch ModelSim, but i get the following error: Apparently it is a license...
View ArticleDDR3 Timings Violation - MAX10 NEEK
Hi there, I tried building a design example (downloaded from the altera cloud service) which is using the DDR3 UniPHY based memory controller. However, if compiled as it is without any changes the...
View ArticleOptimal ALU
Dear all, I'm creating an ALU for a homemade NIOS II compatible processor with Quartus Prime, targeting the Cyclone V. I discovered that, depending on the operations ordering, the ALU has a different...
View ArticleEP2C5T144 mini devboard JTAG issue
I recently owned the http://www.leonheller.com/FPGA/EP2C5T144mini.pdf board, also did some flashes via JTAG. But today, I don't know why, I can't flash via JTAG anymore. I just get the error: Unable to...
View ArticleROM Initialization, Max 10 device 10M02
Hello, I am trying to use a Max 10, 10M02 (2K LEs) device. My design has a ROM, with the Initialization data in a MIF file. However Analysis & Synthesis run fails with the message.. (I am using...
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compiling Linux kernel in cygwin
Hi, Is it possible to compile the Linux kern el in the Cygwin environment? Right now, I am seeing error (see attachment) when I follow instructions to compile Linux kernel from...
View ArticleRegarding POF file format
I'm a IC support engineer. I need to support Altera CPLD(10M08SCU169I7G) to our programmer recently. We need to know the POF file format and integrate it in my programming systems. How to get the...
View ArticleDifference between simulation and real test.
Hi all, I am a student and I am working on a homework. Shortly, I will summary the hw's requirement. It said some thing like that: At first, when counter goes from 0->7 then led 1 on; when the...
View ArticleReading/Writing from/to 16 Mbit Flash RAM (S29AL016M10TAI020)
Hi, I am trying to interact with a 16 Mbit Flash RAM (S29AL016M10TAI020) in Verilog, but I have some problems. This flash supports byte or word mode, I have studied the datasheet and I have tried to...
View Articlegenerate clock after a specific number
hi! I started to learn VHDL,so be patient :) also my english is poor :cool: but I try to explain my problem: I try to emulate a code for generate (and delay it by a precise integer) the clock, but i...
View ArticleAlternative JTAG Programing
Hello Has anyone tried to use a DE1 or similar board as a JTAG programmer for other CPLD /FPGA devices without hacking the board itself, i mean routing the JTAG signals trough the FPGA to the I/O pins...
View ArticleProblem in Generation of write_n, read_n signals in NIOS-II
Dear all, I am facing a peculiar problem while using NIOS. I have written my own custom core, which is having Control register,Status register, Select_reg, TX_register, RX_register and I am trying to...
View ArticleUART using NIOS II
Hi again, I already posted a topic about nios ii altera ans esp8266, I fixed all my problems with the esp8266, now i still struggling with my uart C code, my transmit function works well, but with my...
View ArticleSignalTap II trigger does not work consistently
I am using Quartus Prime version 16. I want to use a very simple trigger. Whatever trigger I select, it does not work consistently. SignalTap sometimes gets stuck on "acquiring pre-trigger data" and...
View ArticleNon-blocking fgets
Hi, I'm interfacing MAX10 fpga development kit with matlab. The matlab sends command to the .c file which in turns request data from the fpga development kit. I'm able to acquire data continuously but...
View ArticleRTL Sequence creation
Hi there people, I'm studying VHDL programing and i'm getting stuck on this question and i have a examination coming up soon, so i'm stressing a little. My question is. A 5-bit signed number (two...
View ArticleRTL sequence to VHDL translation
How would i place this RTL sequence and convert it into VHDL input:clk,mr,x,dat[6] output:rdy,err,resa[3].resb[3] registers;rega[3]. regb[3] sequence: 0. regb<=000 1. rega <=dat [5..3];...
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I'm implementing a Math Equation on my FPGA, am I following the right...
Dear friends, This is my first project ever in FPGA. I'm implementing a Math Equation over a list of numbers (data) which range from 0 - 255, one by one, data can contain 100 or 10.000 or 50.000...
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CIC strange behaviour. Quartus prime 16.0
Dear Sirs and Madams, i try to test CIC ip core. My parameters are: Input Sampling rate 120MSPS System Clock 120MHz Decimation rate 120 Input Channels 16. Problem is core does not generate start of...
View ArticleDE1-SoC Board Connector Mate Question
Hello, I am looking for information about a compatible board-to-board mating connector for the DE1-SoC FPGA board. I am simply going to attach it to a board my team is designing and would like the...
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