Problem in Generation of write_n, read_n signals in NIOS-II

Dear all,
I am facing a peculiar problem while using NIOS. I have written my own custom core, which is having Control register,Status register, Select_reg, TX_register, RX_register and I am trying to write or read these registers using NIOS-IDE, but I am not able to do it. Each of the registers are of 16bit and each of the registers are being configured as Avalon-mm slave devices. In Control register, I am able to write but the same thing I am not able to do in TX and Select registers. When I monitored the 'write_n' and 'read_n' signals in Signal-Tap, I was able to observe 'write_n' signal being generated for Control Register but it is not getting generated for TX and Select registers. Similar is the case with 'read_n' signal, it is also not getting generated and I am ending up reading garbage values for Status Register.

For this I referred in Altera Forum, but I am not able to get any answer. The only answer given was the usage of dynamic addressing instead of native addressing, that I am already doing as I am using IOWR_16DIRECT, IORD_16DIRECT.

I don't know where is the mistake but I suspect it might be during generation by QSYS. Please help me on how to proceed further.

Thanks,
gupnaval