OpenCL Licence with new Altera Board?
I've downloaded the OpenCL SDK however when i compile it tells me "Can't find a valid license for the Altera SDK for OpenCL". Now I have seen this error before on other forum posts, however, I am...
View Articleundefined symbol: __acl__convert_SItoFP_32
Hello, I compiled a .cl file into .aocx in this way: aoc -march=emulator kernel.cl -o kernel.aocx The compilation succeeds. Then I try to create a program from the .aocx file in this way: program =...
View ArticleProblem with Quartus Prime 16.0 Lite Edition.
Hi, Can anyone help me with this issue? Whenever I start compiling my design in Quartus Prime 16.0 Lite Edition, the memory consumption shoots up to 100 % and Quartus becomes " Not Responding". Thanks,
View ArticleDe1-soc adc controller
I have and DE1-SoC rev D. And are trying to use the ADC by the IP Library\University Program\Generic IO\De1-SoC Controller. I read the De1-SoC Controller.pdf file, but it is not enough, I have not been...
View Articleinvert clock at output pin in DDR3 uniphy controller
Hi, I am using DDR3 uniphy controller in startixV(with Quartus 15.1). In PCB board design, the clock is mistakely swaped at output, that is, ck at fpga pin is connected to ck# at ddr3 pin. Is there any...
View ArticleSome basic questions regards Altera Max V
hi, I have a project which using Altera Max V for reading data from a sensor and transmit it to a PC. I'm totally new to FPGA/CPLD as well as Altera Max V and I have some basic questions as following:...
View ArticleConfigure MAX10 CPLD using remote micro CPU
I would configure MAX10 CPLD using remote micro CPU. As I got from the datasheet MAX10 has only JTAG setup, I mean first time MAX10 initialization. I tried to look through the many docs and I found...
View Articleconfusing of device tree blob
hello I have been managing to build whole board specific linux image (the board is DE1-SoC) This is what I understand : linux-socfpga kernel source, which is available at altera-opensource git, is...
View ArticleNon Blocking UART I/O
Hi, I'm not able to implement Non-Blocking I/O. I have made the following changes to make the fgets function Non Blocking : _serialPort = fopen("/dev/uart_0", "r+"); fd = fileno(_serialPort); fcntl(fd,...
View ArticleVTAP Tutorial
Hi, Can someone provide a tutorial on how to use VTAP in the Max10 devkit? Thank You
View ArticleSoftware and IP cost viability for home use
Hello. Similarly to the previous thread, I'd like to check the licence situation for IP cores and Quartus while using the dev boards. I have had a look through the manuals but it is still not clear to...
View ArticleUART in DE 0 nano board
Hello, From where can i get the code for UART for DE 0 Nano board ?
View ArticleLink Aggregation (IEEE 802.3ad) in TCP and Source Specific Multicast in UDP
Hi I am looking for an implementation of: 1.UDP: receive Source Specific Multicast via UDP. SSM is defined in IPv4's IGMPv3. 2. TCP: I have 2 ethernet interfaces which i need to put into LACP (IEEE...
View ArticleMAX10 dual boot, NIOS2 boot from UFM. Not booting.
Hello, I have an issue with a MAX10 (max 10 FPGA Development Kit). I am trying to boot from UFM with a dual boot component in my QSYS System but nothing happens on reset and after programming. For me...
View ArticleReference for Boards Power Button
Hi all, Just a simple question here. I want to design a custom board with FPGA inside. I like the Red power button of my Altera DE1 https://www.altera.com/content/dam/a...ds/de1_soc.jpg Anyone can tell...
View ArticleHelp: Simple Socket Server - Stratix IV GX
Hello, I have a very basic knowledge on FPGAs and Verilog, as I only started to learn about it this semester. my final year project is quite big as I have to implement a PoE structure then make...
View ArticleFIR compiler II syntax error
I am using Quartus 15.1 to generate a FIR II core. I chose the Verilog option for the cores language. I am using Candace tools to elaborate and simulate a design with the generated FIR II core. Here...
View ArticleDe2-115 Development and Education Board Ethernet Socket Manufacturer
Hi, I have DE2-115 dev. board and one of my ethernet sockets have blown up. I just want to replace it with a new one but the part number given in schematic files does not belong to any manufacturer (...
View ArticleFrequency Hopping Spread Spectrum in VHDL
Hello! I am working on a project to design a FHSS system. So far, I have managed to design the PN code generator, but I have some difficulty working on the (Frequency Synthesizer) part. I would be very...
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Design of FHSS using VHDL
Hello everyone. I am currently working on a project to design a (Frequency Hopping Spread Spectrum) system using VHDL language. I am not sure to use VHDL approach or Schematic one. So which one do you...
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