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terasic / Atlas-SoC Kit and Altera OpenCL compatibility
I apologize in advance if this has been asked before. Searched but found no answers. I bought the terasic / Atlas-SoC Kit. According to this document, it works with the OpenCL dev kit from Altera:...
View Articleclarification on Cyclone V transceiver reference-clock data sheet jitter specs
Regarding the Cyclone V data sheet (CV51002, 2016.06.10) Table 20 (page 25): https://www.altera.com/en_US/pdfs/li...v/cv_51002.pdf Q1: Is the Transmitter REFCLK Phase Noise specification defined for...
View ArticleCORDIC vs. Matlab results
Hello, I am using Altera CORDIC for ATan2 and SinCos functions. I am applying the same test vectors to the CORDIC ATan2 and SinCos functions testbench and to the ATan2 and SinCos Matlab Models. I see...
View ArticleSynchronization on falling and rising edges
Hi, I need help . I need to synchronize to the falling and rising edge encoder signal "A" . Both these edges need to work with the signal "count". I have this error : Error (10028): Can't resolve...
View ArticleMake DE0 Nano to be Bootable and use SDRAM to store hardware and software
Hi all, Please help me, I have been stuck with this problem for MONTHS. I am currently working on a Nios II based design using the DE0-Nano board and the on board 32Mb sdram. My system is as follows:...
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DE2 - CFAH1602B-TMC-JP Initialization Sequence
Hello, I have a Terrasic DE2 and am trying to initialize the LCD and then turn on the backlight for confirmation. I've modeled the sequence all the way up to the final point described in the datasheet...
View ArticleCan Virtual Jtag Ip and Uart Jtag Ip work together?
Saw this great post about using quartus_stp.exe on a pc connected to a de0-nano's jtag: http://idle-logic.com/2012/04/15/tal...tag-interface/ The quartus_stp allows network connected devices to...
View Articlebuses name in max+
hello I have 8 16-bit signal, and I want combine them to one signal. A0[15..0] A1[15..0] A2[15..0] . . . A7[15..0] I want convert(or combine) them to this signal : A[7..0][15..0] all of this signals...
View ArticleStoring 8 bit data in SDRAM in DE 0 Nano
Hello, I want to do high speed data acquisition (50 Msps approx.) with my de 0 nano board. I need to store 8 bit data samples in it and transmit it. Though i have managed to perform uart I am not sure...
View Articleoperate UART w/ NIOS wo/ HAL
The following code should make a loopback between UART RX and TX (echo). However, it seems that first N typed chars (from PC towards the board) are not successfully absorbed. After N characters (few...
View ArticleCyclone V: max speed TTL parallel bus on GPIO
Hello! I want to make a high speed 14-bit wide parallel bus (TTL levels) on Cyclone V. What max speed it can be? For example 250 MHz??? I don't have this devise, so i can't test it myself. Sorry for my...
View ArticleMAX-V scalability
Hi, I am going to use MAX-V type 5M570ZF256 on my new board and I would like to upgrade in future to 5M1270ZF256. But I found that each of these two versions has a single GND pin which is not...
View ArticleAltera lab SoC FPGA Linux training
Hello, I apologize if Im in the wrong place. Ive got a DEO-Nano-SoC from Altera/terasic and try to follow an Altera Tutorial which doesnt appear to work very well. Its the SoC FPGA Linux Training...
View ArticleMax V Development KIT 10MHz external clock pin map ?
Hi I'm new to CPLD as well as VHDL. I am going to buy a Max V Developement KIT, and my first project is bulding a time multiplexer. I need to use the 10MHz clock as an input signal for this time...
View Articlebooting nios2 from external OTP memory
Hi, I want to boot nios2 with the external OTP memory. is it possible to boot nios2 from OTP memory, if so what is the interface we can use.Can anyone explain the booting process of nios2 from OTP...
View Articlefast input registers routed over HPS Loan I/O Pins
Hi, I have a Cyclone V SE with a design that includes an SDIO Host Controller IP in order to attach an SDIO WiFi-Module to the System. The SDIO Host Controller IP needs fast input registers. When I try...
View ArticleAlternate for FPGA CycloneV Series
We are using FPGA 5CGXFC4C6F27C7N in our application, which has high speed interfaces, so PCIe hard IP is mandatory, please suggest any low cost alternative to this part.
View ArticleU-boot: USB device communication problems on cycloneV (dwc2)
Hi, I have a CycloneV SoC Development kit, rev D. The builder machine is a Debian 8.5, 64 bit, using Yocto/Poky. I would like to boot the kernel from an external USB mass storage device. Now i have a...
View ArticleExternal memory (A2V64S40CTP, IS61WV25616BLL, S29AL032D70TFIO4)
Hello World I use an old Terasic DE1 board with Cycolne II. Onthis bord have SDRM A2V64S40CTP, SRAM IS61WV25616BLL, and Flash S29AL032D70TFIO4). I work with QuartusII 13.1 I manage to creat SoC with...
View ArticleDHCP times out in ethernet example
I try to run the example "Nios II Ethernet Simple Socket Server on MAX 10 FPGA Development Kit". However, instead of "Acquired IP address via DHCP client for interface: et1¨ in step 7 of the manual I...
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