Hi all, Please help me, I have been stuck with this problem for MONTHS.
I am currently working on a Nios II based design using the DE0-Nano board and the on board 32Mb sdram. My system is as follows:
Windows 10
Quarts V.14.1
Qsys system:
- 50MHz CLK
- CPU
- EPCS Flash Controller
- Onchip memory
- PIO
- SDRAM controller
- JTAG UART
- SysID
- UART
- PIO
Reset and exception vectors have been set to EPCS Flash Controller and SDRAM Controller.
SDRAM is clocked by separated PLL and I have confirmed that the SDRAM works without any problem.
Now I am at the point where I want to load the hardware design and software onto the EPCS so the board can operate in a standalone situation. For more information, I am using a lot of libraries and not using the small c option. So, I need to use SDRAM to store instructions and data for NIOS application. I mention this because the method of programming a bootable system in the de0 nano literature (initializing on-chip memory with program code) is not an option due to the size of my code. I've looked through many posts in the internet regarding this topic. There's a lot of outdated documentation and conflicting forum posts about this process so I was hoping someone could lend me some guidance.
As stated above, there are various information on the internet so I have tried two methods.
The first method is to convert .sof file into .jic file.
Based on this method, I can make the hardware to be bootable easily. Then I tried to make the software to be loaded by the method in the below link.
http://geobyjmhembeddedengineer.blog...-directly.html
I can program the .jic file into the board. The hardware becomes bootable but the software does not load after the board reset.
It caused me to doubt that whether this first method can not be used together with SDRAM so I tried the second method.
In the second method, I added EPCS Flash Controller. Set Reset and exception vectors to EPCS Flash Controller and Onchip Memory.
I have done everything that is described here.
https://sites.google.com/site/fpgaan...sII-standalone
But the result is error message when I try t do the flash programming as shown below.
https://dl.dropboxusercontent.com/u/153995/error.png
According to many threads, this error is caused by the new Scansion chip in the board and can be solved by adding a patch file into the bin directory in nios2eds folder.
I have done it but the error still appears.
I am very confuse now. Sorry for my noobness. Hope someone can help me, please.
Thank you in advanced.
You can download my project from here.
https://dl.dropboxusercontent.com/u/...1s_Yossiri.zip
Could you try it whether it is work on your computer?
I am currently working on a Nios II based design using the DE0-Nano board and the on board 32Mb sdram. My system is as follows:
Windows 10
Quarts V.14.1
Qsys system:
- 50MHz CLK
- CPU
- EPCS Flash Controller
- Onchip memory
- PIO
- SDRAM controller
- JTAG UART
- SysID
- UART
- PIO
Reset and exception vectors have been set to EPCS Flash Controller and SDRAM Controller.
SDRAM is clocked by separated PLL and I have confirmed that the SDRAM works without any problem.
Now I am at the point where I want to load the hardware design and software onto the EPCS so the board can operate in a standalone situation. For more information, I am using a lot of libraries and not using the small c option. So, I need to use SDRAM to store instructions and data for NIOS application. I mention this because the method of programming a bootable system in the de0 nano literature (initializing on-chip memory with program code) is not an option due to the size of my code. I've looked through many posts in the internet regarding this topic. There's a lot of outdated documentation and conflicting forum posts about this process so I was hoping someone could lend me some guidance.
As stated above, there are various information on the internet so I have tried two methods.
The first method is to convert .sof file into .jic file.
Based on this method, I can make the hardware to be bootable easily. Then I tried to make the software to be loaded by the method in the below link.
http://geobyjmhembeddedengineer.blog...-directly.html
I can program the .jic file into the board. The hardware becomes bootable but the software does not load after the board reset.
It caused me to doubt that whether this first method can not be used together with SDRAM so I tried the second method.
In the second method, I added EPCS Flash Controller. Set Reset and exception vectors to EPCS Flash Controller and Onchip Memory.
I have done everything that is described here.
https://sites.google.com/site/fpgaan...sII-standalone
But the result is error message when I try t do the flash programming as shown below.
https://dl.dropboxusercontent.com/u/153995/error.png
According to many threads, this error is caused by the new Scansion chip in the board and can be solved by adding a patch file into the bin directory in nios2eds folder.
I have done it but the error still appears.
I am very confuse now. Sorry for my noobness. Hope someone can help me, please.
Thank you in advanced.
You can download my project from here.
https://dl.dropboxusercontent.com/u/...1s_Yossiri.zip
Could you try it whether it is work on your computer?