triple speed ethernet upgrading to nios ii/f problem
Hi, I am working on a project on a DE2-115 board that involves both a NIOS processor and the triple speed Ethernet IP core , the problem is that NIOS ii/e processor works well with the mentioned IP...
View ArticleDe1-SoC Linux Ubuntu Desktop - quartus project
Hi I have De1-Soc board and I downloaded Linux Ubuntu Desktop image from 2015-06-26. If I set MSEL to 00000 it runs properly but If I want to configure FPGA from Quartus (I use DE1_SOC_Linux_FB...
View ArticleResize function not working
I'm trying to use the resize function in order to convert a signed 12 bit value to a 31 bit value. But whenever I'm using the resize function the output value is 0. But when I'm manually converting it,...
View ArticleRead data from an Ax-12 actual
Hi everyone, I'm using this servo: http://www.hizook.com/files/users/3/..._UserGuide.pdf Using a DE2 and a few modules I wrote in VHDL, I send it commands (called an instruction packet) and it sends...
View ArticleHard Copy ASIC for MAX 10 FPGA Design
I am interested in getting hardcopy ASIC out of MAX10 FPGA implemented design. The proof of concept is validated in MAX10 FPGA & for production the volume can be around 10K units. The processing...
View Articleerror detection crc
Hi , For SEU mitigation in Stratix iv GX device, I enabled ''Enable error detection CRC" from Device and Pin Options in Quartus II 13.1. But while synthesis got the error message that " Error(21216):...
View Articledigital filter
hello everybody. i am beginning with vhdl an i try to implement a digita filter on cyclone 2 This is the code i havebut i d ont understand why it doesnt work thk for help library IEEE; use...
View ArticleStratix 10 ?'s
Hello, I've been anxiously waiting the release of the Stratix 10 for quite some time. Does anyone know when the Stratix 10 will start shipping and when a dev kit will be available? Thanks, Joe
View ArticleSOC Tools: Is Xlinx light-years ahead of Altera?
Hello, I was reading another forum post where someone stated that Xilinx SoC development tools where light-years ahead of Altera and I wanted to post such a question. Are Xilinx Soc development tools...
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Trouble with CIC filter
I'm trying to implement a CIC decimation filter( with R = 1000, M = 1 and N = 2 ) and Fs = 1 MHz without using the CIC IP core. Using matlab implementation I found out that the suppression of the CIC...
View ArticleReflexces XpressGX5-LP SE
We have the PCIE Board XpressGX5-LP SE with Startix V. https://www.reflexces.com/products/b...pressgx5-lp-se I create QSYS system based on the Altera example QSYS project for Stratix V PCIE. But this...
View ArticleHow to interface FFT core with I/O
I am working an application that involves reading in an analog signal and performing a 4k FFT on the signal. I have read the FFT megacore pdf and can generate standalone FFT files with the parameters I...
View ArticleQuartus pauses between A&S, Fitter and Assembler
Hey, recently quartus seems to behave quite strange for my project. All of a sudden compiling takes much more time and i have the feeling that quartus pauses between the Analysis & Synthesis,...
View ArticleArria V 64-Bit multiplication
I noticed while running Quartus timing analysis on a simple 64x64 bit multiplication (with 2 pipeline stages) on the Arria V board that I was getting very low Fmax values. Looking into the Chip Planner...
View ArticleArria 10 Soc FFT?
Hello, I have a design that implements an FFT on a Stratix FPGA I'm thinking about a new design using the Arria 10 SoC FPGA. In my new design I was thinking about moving the FFT operations onto the...
View ArticleniosII 16.0 Software build tools and windows 10
Hello! Do The software niosII 16.0 Software build tools (eclipse) is compatible with Win 10? Do has anyone tried? Regards, Luca
View ArticleCyclone V and Security
Hi there, I have a question about the Cyclone V security feature. As far as I know the security feature of Altera's FPGA's is used to protect the design of the FPGA from being copied or reverse...
View ArticleFIFO IP is getting empty at a faster rate
Hi, I'm using a FIFO IP with width of the fifo being 16 bit and the depth of the fifo buffer is 16384 words. I'm using the MAX10 development kit and interfacing it with Matlab. The baud rate is set to...
View ArticleBEMICRO MAX10 Altera SDRAM controller from QSYS
I'd like to export the Altera Avalon-MM SDRAM controller from QSYS on my BEMICRO MAX10 FPGA eval board. I won't be using NIOS-II, but my own (and open-source) custom verilog hardware. The plan is to...
View ArticleError: (vsim-3828) Could not link vsim_auto_compile.dll
Good Morning, I created a system by means of the Quartus Qsys composed by a SoC (hard processor system - hps) and an Avalon Slave. The Qsys generated all the files for synthesis and simulation,...
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