Another "registers lost all their fanouts during netlist optimizations" confusion

Hi,

Another VHDL, Quartus and FPGA newbie. I'm not a student, graduated in microelectronics systems engineering > 20 years ago; this is new a hobby.

I've created my own little "CPU". Works fine under ModelSim. I now want to upload it to my FPGA but notice that I have the newbie problem "Total Logic Elements 0" and the warning "Info (17049): 296 registers lost all their fanouts during netlist optimizations."

I've seen previous suggestions to "ensure that the top level entity drives some output". As far as I can tell, that's what I'm doing, as I have some output signals in the top entity.

Obviously I'm getting something fundamentally wrong, and I'd really appreciate some pointers. Was looking forwards to flashing some LEDs :cry:

I've attached my VHDL code and the map.rpt output file.

If it makes any difference the target device is an EP2C5T144-8 on a DigiASIC board, and I am using Quartus 12.1 32bit under Windows 7 64bit.

Thank you,

Mark

Attached Files

• CPU_1 v0.4.vhd (6.1 KB)
• CPU_1.map.rpt.txt (128.5 KB)