License problem
Hi ! I am new at altera FPGA devices.I have a quartus 2 web edition.As I read from altera documents, after relasing the 8.1 version of quartus program,there is no license file for web edition quartus....
View ArticleStart and done ports of multicycle custom instruction
Hi everyone, I have read through the NIOS II Custom Instruction User Guide and there is one thing I am not really clear about: For a variable multicycle custom instruction, the ci master asserts start...
View ArticleSimulating with ModelSim> Will it simulate megafunctions in AHDL?
Hi, I must move from the Quartus Simulator to ModelSim and I have a question about simulating with AHDL. Will ModelSim simulate User written AHDL files? Will ModelSim simulate megafunctions based on...
View ArticleWQFN148 Usage Restriction -- 32 mil PCB thickness
We're using an EP4CGX15BN11C7N Cyclone IV device in a WQFN148 package on an extremely tiny board. The mechanical definition document states that the part shouldn't be used in boards more than 32 mils...
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Multiprocessor problem
Hi, I m till now at the some problem with the multiprocessor tutorial :mad: , I have applied the tutorial with the cynlone 2 De2_70 board, and Stratix 2, 2S60ES board. after generation and compilation...
View ArticleBoundary Scan Test for EPM240T100
I have been using the EPM240T100 part for a long time but never had the need to ask this question. I have looked in the Altera website for everything related to my question but have not found an...
View ArticleAvalon MM Slave Query
Hey Everyone, For a university project I'm trying to implement a custom hardware block to help accelerate the calculation of the determinant of a matrix. We're using Quartus V12, and a TerASIC DE0...
View ArticleMy DE2-115 cyclone IV E is not powering up when i switch on.
My DE2-115 cyclone IV E is not powering up when i switch on. I have checked for proper connections, power supply etc. I got it two weeks back so its brand new. I did not notice any burnt smell or smoke...
View Articleneed helps in coding...
hi i'm using an ultrasonic sensor to measure distance which produces PWM output, the pwm output is 147us/inch. i want to implement it in de2 board. i'm using 50MHz input clock from de2 board and the...
View Articlecontent addressable memory
is there any way to have content addressable memory(CAM) in CYCLONE IV E families????
View ArticleRunning ModelSim in command-line mode
Hi, I write a testbench name test_FA.v. In the comman prompt, i go to test_FA.v directory and taip 1) vlib work 2) vlog test_FA.v. 3) vsim -c -do FA_run_msim_rtl_verilog.do FA -wlf waveform.wlf...
View ArticleDE0 FPGA board , how to connect it to another FGPA wirelessly using two xbee...
can someone tell if it's possible to make two fpga's to communicate and send data without cables using two Xbee pro sensors ?? and if it's possible can you assist me in doing that , like writing codes...
View ArticleReccomendation for simple SD card (SPI mode) for DE0-nano
Hi All, I have been working through various attempts to get FAT16 attached via an SD card to a NIOS processor. All I need to do is to quickly load a 10MB file from SD media into SDRAM once, at power...
View Articlemaximum clock speed for cyclone iv
hello everyone, we have bought a de0-nano board for our project. it has an 50 mhz clock. what i want to ask, what is the maximum clock rate to apply cyclone iv externally? or, more clear, can we apply...
View Articleexporting system verilog functions and task to C using DPI
hello, I have been trying to import and export functions and task through DPI between system verilog and C. I have managed to import functions and task from C to SV:) but can't really figure out how to...
View ArticleRedirection with NiosII Web Server Demo Altera DE2
Hi, I'm came to the DE2 from a Netburner and Coldfire board where the web server was provided and allowed function calls like "RedirectSocket". But I'm trying to use the Web Server demo provided in the...
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DE2_NET lab demonstration nios IO communicating error
i tried the lab demo an encountered some error, im not sure how to solve it. Anybody got an idea? Attached Images IO communication error.jpg (85.0 KB)
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Another "registers lost all their fanouts during netlist optimizations"...
Hi, Another VHDL, Quartus and FPGA newbie. I'm not a student, graduated in microelectronics systems engineering > 20 years ago; this is new a hobby. I've created my own little "CPU". Works fine...
View ArticleInternal Error during Fitter (Place & Route) when compiling a PCIe x1 demo
Hello all, First time poster, thanks in advance for reading. I'm experiencing an Internal error during the Fitter (Place and Route) stage and it's 100% reproducible with no obvious workaround. Stack...
View ArticleVIP: clocked video input, frame buffer and clocked video output
I am using the tPad development board from Terasic. The CCD outputs 1920 x 1080 @ 30fps, clocked with 96MHz. The video then enters the SOPC etc. As a reference, I want also to see the original video on...
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