Quartus 6.0 software cant be downloaded
The software cannot be downloaded, it states at the website that the "file not found". Any ideas where can i get this 6.0 version. I need it to run DE2_WEB.rar demo on DE2 board.
View ArticleNIOS-II Response to External Interrupt
Hello Frined's, My Nios-ii System taking continuous interrupt at 1 mhz from external FPGA module with in same FPGA (Altera DE2_115 board), but when i forwarding this interrupt signal on another...
View ArticleDDR2 SDRAM with UniPHY not generating half_rate_clock
Hi there, I'm using Quartus 12.1 SP1 and generated a DDR2 SDRAM Controller with UniPHY via the MegaWizard Plugin Manager. The Memory Frequency is 400 MHz, PLL reference clock 50 MHz and the Rate on the...
View ArticleNIOS2 Clock Source?
Hi all, I am trying to use a Nios2 Processor on my custom designed board of Cyclone iv GX. I have an external 125Mhz diff clk. Can i use a PLL inside my FPGA, Using the above external crystal as clock...
View ArticleAvalon: readdatavalid is TWO?!
Hi everyone, without even sending any read or write requests to the SDRAM Avalon Slave, I get a readdatavalid = 2, for it... How can a 1 bit wide signal become two anyway? Many thanks in advance.
View ArticleProblem with burstcount > 2 for Avalon MM Master to SDRAM
Hello, I am trying to implement a burst transcation with SDRAM using Avalon MM Interface. The following Verilog code works fine for burstcount = 2: Code: module hw_det_3by3( Â Â clk, Â Â reset,...
View ArticleHow to reduced intradomain skew in Alter FPGA!
I am implementing my design into Stratix IV with PMA direct mode transceiver. I got following suggestion while analyzing setup violation. Place source and destination clock on the same global clock...
View ArticleIs there any document describing Altera Jtag components?
I find the component **_jtag in the library of Quartus, but cann't find detailed information about it. The component is as below: component cyclone_jtag generic ( lpm_hint : string := "UNUSED";...
View ArticleAbout PCI Express design
We plan to use ALTERA device to design PCIE data collection board. The hardware design is ok for us, but how to design PCIE's driver and how to design PCIE application software and test tool? Anyone...
View Articleproblem in Writing EPCS64 Through FPGA
Hello, I have a Cyclone III board with EPCS64 on board. I am implementing the remote update. I want to write the application image at particular address (e.g. 0x3D0000) in EPCS. I have generated .rpd...
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To enable the any block
Hi, I am using VHDL for FPGA board. I want to enable any block. But when I am not enable to block, the block still operates. Where am I doing wrong. The simple VHDL code is shown in below. Simulation...
View Article12.0sp2_263_programmer_windows and 12.0sp2_263_quartus_free_windows
What is the difference between them and their usage .details please??? :(
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uClinux MMU, DEO Nano
Hello, We wish to install uClinux MMU on a DE0 Nano. After loading during decompilation on the DE0 Nano uClinux (nios2-teminal) we are faced with a crash "calibrating delay loop" Do you know where can...
View ArticleHow to Load .pof file into M25P406MNP
I am using EP3C25E14417N and M25P40 as the flah memory for this device. I am having .pof program file for altera EPCS4 and I want to load that file into M25P40 (since it is an alternate for EPCS4).The...
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DDR2 RAM with ALTMEMPHY Conroller ?
Hi all, I am trying to initialise my DDR2 ram(MT47H128M16RT-25E) in a custom designed board with a cyclone iv FPGA(). I am using ALTMEMPHY controller to connect to the external DDR2 SDRAM but it is not...
View ArticleNios eds
Hii, I started using DE1 board as part of my BTP Project. I have also installed 12.0sp2_263_quartus_free_windows . This is a 32 bit version. My PC is 64 bit version. My doubts are 1)There is altera...
View ArticleCyclone III Remote update controller on Cyclone IV E
Hi all, I want to use in my Cyclone IV project in SOPC Builder the "cyclone III Remote update controller". Did anyone know if it works? Thanks! regards, Adrian
View ArticleSPI with NIOS2 in qsys
Hi, I want to implement SPI in Qsys with one side NIOS 2. Well in SPI core of altera there is a function " int alt_avalon_spi_command(alt_u32 base, alt_u32 slave,alt_u32 write_length,const alt_u8*...
View ArticleRTL simulation on Quartus II
Dear all, I am getting the following error messages every time I run RTL simulation from Quartus II software: # -- Loading package STD_LOGIC_UNSIGNED # ** Error: (vcom-11) Could not find...
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Input I/O to ARRIA V GX PLL
Hello, I have a 100Mhz clock input to ARRIA-V GX device. this clock input connected to the negative input clock I/O - CLK0N_AP31/DIFFIO_RX_B2N. This clock is driven to a PLL (integer PLL). Is it...
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