pin assignment HSMC with cyclone ii DSP kit
Hi every one I 've problem with DDFS design connect to DAC HSMC there is no anlog signal on the Oscilloscope. all the pin assignment was done and the HSMC was coupled to the cyclone iii DSP kit (is the...
View ArticleError (10327): undefined operator ""=""
Hello guys, it's been a really long time for me without coding in VHDL. I need a stepper motor controller for my nios2 based project so i thought it's best to implement it in FPGA which led me to write...
View ArticleSginalTap: Some nodes not listed in NodeFinder?!
Hi everyone, I am using SignalTap to monitor the runtime-signals of my verilog design. However, I just have the situation, that after compiling the whole design in Quartus and when I want to add...
View Articlereading video using vhdl
hii.. I want to read video through my vhdl code and get its frames for further processing(calculating each frame's mean, standard deviation covarience).. i've no idea how to start.. i thought of using...
View Articleusing GPIO on DE2 board
hi, currently i'm doing a project using a sensor which has pwm output. i'm already done the coding to read the pwm output. i would like to connect the pwm output from the sensor ti de2 board as input....
View ArticleCPLD Newbie
Hi, An older EE here who has NEVER done anything with CPLDs. I know nothing! :) Is there a good book or somewhere on the web that shows where to start? I have a very basic circuit that I would like to...
View Articlemissing vertical sync signal on clocked video output Core
The video IP core I am working on is working. But there is one problem, the output vertical sync signal is missing from clocked video output Core. Please help me to find what is the reason of this...
View Articlevertical sync signal is missing on clocked video output Core
The video IP core I am working on is working. But there is one problem, the output vertical sync signal is missing from clocked video output Core. Please help me to find what is the reason of this...
View ArticleWhat is usage of "generate" in Verilog?
I am confused by the usage of "generate" in Verilog. I checked it online, find some demo codes like: genvar index; generate for (index= 0;index < 64;index = index+1) begin : dq_delay WireDelay # (...
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Can't program the S2GX device with sof file
After compile, if auto detect is clicked: 1.jpg so I added the sof file to the S2GX device, I dont think i should add it to EPM570, right? only pof goes there, right? 2.jpg but when i try to program...
View ArticleIs it possible to write a design over PCIe into Flash?
Hi everyone, I have the following problem: I'm working on a device with a JTAG interface which is only accessable while the device is outside its case. Once it is in its case the JTAG interface isn't...
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Question about FSM registered output logic
Hello, Suppose I've got the following code for registered output logic: ************************** always 'at'(posedge clk) begin if (state == some_state) begin output <= a; end end...
View ArticleSimple hardware for Endat 2.2 implementation
Hello, I recently received an optical encoder from Heidenhain. It works with the Endat 2.2 protocol. I would like to use this encoder with a dSpace station, using parallel I/O connection. After some...
View ArticleThe microc don't do anothers tasks
Hi, I was reading the example code "hello_ucosii.c", but when I modify the code he made only the task1. My code modified is: Code: #include <stdio.h> #include "includes.h" #include "system.h"...
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VHDL help
Hello everyone, i am new here this is my first post =) i really need some help this is for school, and am asked to write data parity check for NOC but i don't know what to do so please help me, here i...
View Articlelogarithmic number system and floating point system convert to verilog coding
now im doing a project of hybrid logarithmic number system for addition and multiplication arithmetic unit. 1. i have two input of real number. eg.: input A=1.342, input B=2.567 2. select the...
View ArticleWhat is the best HDL language for the future: VHDL, Verilog or System Verilog?
Hello, which language is the best to learn for the future of FPGA design Verilog, VHDL or System Verilog? Or, is there something else that will replace the current languages? thanks, joe
View Articlehow can we enable and disable the particular modules we need in verilog?
i need to enable a particular module when some condition is satisfied and each module is selected on particular condition...i have written different modules now and i need to write a top module to...
View ArticleHelp using DE2-115 with 640x480 pixel buffer with back buffer?
Hi I'm developing an audio-visualization system for my undergraduate project. I'm working the media computer example and have made some modifications to the hardware to make the SRAM frame buffer...
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