Hi everyone,
I have the following problem:
I'm working on a device with a JTAG interface which is only accessable while the device is outside its case. Once it is in its case the JTAG interface isn't accessible anymore.
This is why I thought about a design, which is able to connect the PCIe-HIP with the flash-memory of my FPGA. By this way it should be possible to write the Flash-File directly from the PC into the Flash-Memory via the PCIe-Interface.
I know, the first Design has to be programmed using the JTAG-Interface, but this is no problem. I just want to have a tool to change the design afterwards.
Did already someone have the same problem? What do I need to write the File into the Flash-Memory? Are there already any design-examples or IP-Cores?
Currently I'm developing on the Arria II GX Development Kit.
Thanks for reading
Steffen
I have the following problem:
I'm working on a device with a JTAG interface which is only accessable while the device is outside its case. Once it is in its case the JTAG interface isn't accessible anymore.
This is why I thought about a design, which is able to connect the PCIe-HIP with the flash-memory of my FPGA. By this way it should be possible to write the Flash-File directly from the PC into the Flash-Memory via the PCIe-Interface.
I know, the first Design has to be programmed using the JTAG-Interface, but this is no problem. I just want to have a tool to change the design afterwards.
Did already someone have the same problem? What do I need to write the File into the Flash-Memory? Are there already any design-examples or IP-Cores?
Currently I'm developing on the Arria II GX Development Kit.
Thanks for reading
Steffen