Hello,
Suppose I've got the following code for registered output logic:
**************************
always 'at'(posedge clk)
begin
if (state == some_state) begin
output <= a;
end
end
**************************
I thought I would expect something like the following:
绘图9.jpg
but instead waveform in modelsim was like:
绘图10.jpg
I suspect the reason has something to do with using IF statement, but why? Any suggestion will be appreciated.
Suppose I've got the following code for registered output logic:
**************************
always 'at'(posedge clk)
begin
if (state == some_state) begin
output <= a;
end
end
**************************
I thought I would expect something like the following:
绘图9.jpg
but instead waveform in modelsim was like:
绘图10.jpg
I suspect the reason has something to do with using IF statement, but why? Any suggestion will be appreciated.